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BR-112021020832-B1 - Integrated circuit for driving multiple fluid actuation devices, inkjet cartridge, and method for accessing a primary and secondary memory of a fluid ejection device.

BR112021020832B1BR 112021020832 B1BR112021020832 B1BR 112021020832B1BR-112021020832-B1

Abstract

Fluid Ejection Devices Including a First Memory and a Second Memory. An integrated circuit for actuating a plurality of fluid actuation devices includes a plurality of first data lines, a second data line, a first memory element, and a second memory element. The first memory element is enabled in response to the first data in the plurality of first data lines. The second memory element is enabled in response to the second data in the second data line.

Inventors

  • BOON BING NG

Assignees

  • HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P

Dates

Publication Date
20260310
Application Date
20190419

Claims (15)

  1. 1. Integrated circuit for association with a fluid ejection device comprising a plurality of fluid actuation devices, the integrated circuit characterized in that it comprises: a first memory element (112) and a second memory element (114) in at least one array that does not include the fluid ejection device; a plurality of first data lines (D11-3); a second data line (D2); an ID line (ID); a first selection line (S4); and a second selection line (S5); the first memory element (112) configured to be enabled in response to the first data in the plurality of first data lines (D11-3) and in response to a first logic level in the first selection line (S4); and the second memory element (114) configured to be enabled in response to the second data in the second data line (D2) and in response to a first logic level in the second selection line (S5) and a first logic level in the ID line (ID).
  2. 2. Integrated circuit, according to claim 1, characterized in that it further comprises: a shift register decoder (134) configured to enable the first memory element (112) in response to the first data in the plurality of first data lines (D11-3).
  3. 3. Integrated circuit, according to claim 1 or 2, characterized in that it further comprises: a transistor (414) configured to enable the second memory element (114) in response to second data on the second data line (S5).
  4. 4. Integrated circuit, according to claim 3, characterized in that it further comprises: another transistor (324) configured to enable the second memory element (114) in response to the first logic level on the ID line (ID), the transistor (414) located on a first side of the second memory element (114) and the other transistor (324) located on a second side of the memory element (114) opposite the first side of the second memory element (114).
  5. 5. Integrated circuit, according to any one of claims 1 to 4, characterized in that it comprises: wherein the first memory element (112) is accessed via the ID line with the first memory element (112) enabled, and wherein the second memory element (114) is enabled in response to the second data on the second data line (D2) and a first logic level on the ID line.
  6. 6. Integrated circuit, according to claim 5, characterized in that it further comprises: a trigger line electrically coupled to the second memory element (114), wherein the first memory element (112) is accessed by means of the ID line with the first memory element enabled (112), and wherein the second memory element (114) is accessed by means of the trigger line with the second memory element enabled (114).
  7. 7. Integrated circuit, according to any one of claims 1 to 6, characterized in that it further comprises: an address generator (136) configured to generate an address signal; wherein the second memory element (114) is configured to be enabled in response to the address signal.
  8. 8. Integrated circuit, according to any one of claims 1 to 7, characterized in that it further comprises: a plurality of transistors (402, 404, 406) configured to enable the first memory element (112) in response to the first data in the plurality of first data lines (D11-3).
  9. 9. Integrated circuit, according to any one of claims 1 to 8, characterized in that it further comprises: a discharge path (256) electrically coupled between the second memory element and a common or ground node (152); wherein the discharge path (256) is configured to be disabled in response to the first logic level on the ID line and to be enabled in response to a second logic level on the ID line.
  10. 10. Integrated circuit, according to claim 9, characterized in that it further comprises: a transistor (414) coupled to the second selection line (S5) and to the discharge path, the transistor configured to enable and disable the discharge path in response to different logic levels on the second selection line (S5).
  11. 11. Integrated circuit, according to any one of claims 1 to 5, characterized in that the first memory element (112) comprises a non-volatile memory element and the second memory element (114) comprises a non-volatile memory element.
  12. 12. Inkjet cartridge, characterized in that it comprises a print head including an integrated circuit as defined in any one of claims 1 to 11.
  13. 13. Method for accessing a first memory element (112) and a second memory element (114) of an integrated circuit for association with a fluid ejection device, the first (112) and second (114) memory elements in at least one array that does not include the fluid ejection device, the method characterized in that it comprises: sequentially generating a first selection signal and a second selection signal; enabling a first memory element (112) in response to the first selection signal and first data in a plurality of first data lines (D11-3); and enabling a second memory element (114) in response to the second selection signal and second data in a second data line (D2).
  14. 14. Method according to claim 13, characterized in that it further comprises: generating an address signal, wherein enabling the second memory element (114) comprises enabling the second memory element (114) in response to the second selection signal, the second data in the second data line (D2) and the address signal.
  15. 15. Method, according to claim 13 or 14, characterized in that it further comprises: accessing the first memory element (112) through the ID line with the first memory element (112) enabled; and accessing the second memory element (114) through a trigger line with the second memory element (114) enabled.

Description

Background [0001] An inkjet printing system, as an example of a fluid ejection system, may include a print head, an ink supply that provides liquid ink to the print head, and an electronic controller that controls the print head. The print head, as an example of a fluid ejection device, ejects droplets of ink through a plurality of nozzles or orifices and toward a printing medium, such as a sheet of paper, so as to print on the printing medium. In some examples, the orifices are arranged in at least one column or array so that the properly sequenced ejection of ink from the orifices causes characters or other images to be printed onto the printing medium as the print head and the printing medium are moved relative to each other. Brief Description of the Drawings [0002] Figure 1 is a block diagram illustrating an example of a fluid ejection system. [0003] Figure 2 is a schematic diagram illustrating an example of a fluid ejection device. [0004] Figure 3 is a block diagram illustrating an example of a circuit including a first memory and a second memory of a fluid ejection device. [0005] Figure 4 is a block diagram illustrating another example of a circuit including a first memory and a second memory of a fluid ejection device. [0006] Figure 5 is a schematic diagram illustrating an example of a circuit including a memory element of a fluid ejection device. [0007] Figure 6 is a schematic diagram illustrating another example of a circuit including a memory element of a fluid ejection device. [0008] Figure 7A is a schematic diagram illustrating an example of a circuit including a plurality of memory elements of a fluid ejection device. [0009] Figure 7B is a schematic diagram illustrating another example of a circuit including a plurality of memory elements of a fluid ejection device. [0010] Figures 8A-8B are schematic diagrams illustrating an example of a circuit including a plurality of memory elements and a plurality of fluid actuation devices of a fluid ejection device. [0011] Figure 9A is a schematic diagram illustrating an example of a circuit including a first memory, a second memory, and fluid actuation devices. [0012] Figure 9B is a schematic diagram illustrating another example of a circuit including a first memory, a second memory, and fluid actuation devices. [0013] Figures 10A and 10B are timing diagrams that illustrate an example of the operation of the circuit in Figure 9B. [0014] Figures 11A and 11B are timing diagrams that illustrate another example of the operation of the circuit in Figure 9B. [0015] Figure 12 is a block diagram illustrating an example of a fluid ejection system. [0016] Figures 13A-13D are flow diagrams that illustrate an example of a method for accessing a first memory and a second memory of a fluid ejection device. [0017] Figures 14A-14B are flow diagrams that illustrate an example of a method for accessing a fluid ejection device memory. [0018] Figures 15A-15B are flow diagrams that illustrate another example of a method for accessing a fluid ejection device memory. Detailed Description [0019] In the following detailed description, reference is made to the accompanying drawings which form a part of this document, and which are shown by way of illustration of specific examples in which the disclosure may be practiced. It should be understood that other examples may be used and structural or logical changes may be made without departing from the scope of this disclosure. The following detailed description, therefore, should not be taken in a limiting sense and the scope of this disclosure is defined by the appended claims. It should be understood that the features of the various examples described in this document may be combined, in part or in whole, with each other, unless specifically indicated otherwise. [0020] As used in this document, a "logic high" signal is a logic "1" or "on" signal, or a signal with a voltage approximately equal to the logic power supplied to an integrated circuit (for example, between about 1.8 V and 15 V, such as 5.6 V). As used in this document, a "logic low" signal is a logic "0" or "off" signal, or a signal with a voltage approximately equal to a logic power ground return for the logic power supplied to the integrated circuit (for example, about 0 V). [0021] A print head for use in a printing system may include nozzles that are activated to cause droplets of printing fluid to be ejected from the respective nozzles. Each nozzle includes a fluid actuation device. The fluid actuation devices, when activated, cause a droplet of printing fluid to be ejected from the corresponding nozzles. In one example, each fluid actuation device includes a heating element (e.g., a thermal resistor) that, when activated, generates heat to vaporize a printing fluid in a firing chamber of a nozzle. The vaporization of the printing fluid causes the expulsion of a droplet of printing fluid from the nozzle. In other examples, each fluid actuation device includes a piezoe