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BR-112021020903-B1 - Integrated circuit for driving multiple fluid actuation devices, inkjet cartridge, and method for accessing the memory of a fluid ejection device.

BR112021020903B1BR 112021020903 B1BR112021020903 B1BR 112021020903B1BR-112021020903-B1

Abstract

FLUID EJECTION DEVICES INCLUDING A MEMORY. An integrated circuit for actuating a plurality of fluid actuation devices includes a trigger line, a plurality of memory elements, a first switch, and a plurality of second switches. The first switch is electrically coupled between the trigger line and the first side of each memory element of the plurality of memory elements. Each second switch is electrically coupled to the second side of a respective memory element of the plurality of memory elements.

Inventors

  • BOON BING NG

Assignees

  • HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P

Dates

Publication Date
20260310
Application Date
20190419

Claims (11)

  1. 1. Integrated circuit for actuating a plurality of fluid actuation devices (352), the integrated circuit characterized in that it comprises: a trigger line (TRIGGER); a plurality of memory elements (214); a first switch (324) electrically coupled between the trigger line (TRIGGER) and a first side of each memory element (214) of the plurality of memory elements (214); and a plurality of second switches (328), each second switch (328) electrically coupled to a second side of a respective memory element (214) of the plurality of memory elements (214).
  2. 2. Integrated circuit, according to claim 1, characterized in that it further comprises: an ID line (ID); wherein the first switch (324) is to turn on in response to a first logic level on the ID line (ID) and turn off in response to a second logic level on the ID line (ID).
  3. 3. Integrated circuit, according to claim 1 or 2, characterized in that it further comprises: a decoder (360) for receiving an address and for turning on a respective second switch (328) of the plurality of second switches (328) in response to the address.
  4. 4. Integrated circuit, according to any one of claims 1 to 3, characterized in that it further comprises: a plurality of fluid actuation devices (352); and a plurality of third switches (358), wherein each fluid actuation device (352) of the plurality of fluid actuation devices (352) is electrically coupled between the trigger line (TRIGGER) and a respective third switch (358) of the plurality of third switches (358).
  5. 5. Integrated circuit, according to any one of claims 1 to 4, characterized in that each first switch (324) comprises a transistor.
  6. 6. Integrated circuit, according to any one of claims 1 to 5, characterized in that each second switch (328) comprises a transistor.
  7. 7. Integrated circuit, according to any one of claims 1 to 6, characterized in that each memory element (214) of the plurality of memory elements (214) comprises a non-volatile memory element.
  8. 8. Inkjet cartridge, characterized in that it comprises a print head including an integrated circuit as defined in any one of claims 1 to 7.
  9. 9. Method for accessing a memory (214) of a fluid ejection device, the method characterized in that it comprises: electrically connecting, by means of a first switch (324), a first side of each memory element (214) of a plurality of memory elements (214) to a trigger line (TRIGGER) in response to a first logic level on an ID line (ID) and electrically disconnecting, by means of the first switch (324), the first side of each memory element (214) of the plurality of memory elements (214) from the trigger line (TRIGGER) in response to a second logic level on the ID line (ID); to electrically connect, by means of a respective second switch (328) of a plurality of second switches (328), a second side of a respective memory element (214) of the plurality of memory elements (214) to a common node (152) in response to an address signal.
  10. 10. Method according to claim 9, characterized in that the first switch (324) comprises a first transistor, and in that the plurality of second switches (328) comprises a plurality of second transistors.
  11. 11. Method, according to claim 9 or 10, characterized in that it further comprises: accessing a respective memory element (214) from the plurality of memory elements (214) by means of the trigger line (TRIGGER) with the respective memory element (214) electrically connected between the trigger line (TRIGGER) and the common node (152).

Description

BACKGROUND [001] An inkjet printing system as an example of a fluid ejection system may include a print head, an ink supply that provides liquid ink to the print head, and an electronic controller that controls the print head. The print head, as an example of a fluid ejection device, ejects droplets of ink through a plurality of nozzles or orifices and toward a printing medium, such as a sheet of paper, in order to print on the printing medium. In some examples, the orifices are arranged in at least one column or set in such a way that appropriately sequenced ejection of ink through the orifices causes characters or other images to be printed onto the printing medium as the print head and the printing medium are moved relative to each other. US8864260 discloses an erasable programmable read-only memory (EPROM) integrated circuit (IC) structure for a thermal inkjet printhead including a trigger line to provide trigger line data, a select line to provide selection data, a trigger cell coupled to the trigger line, an EPROM cell coupled to the trigger line, a select cell coupled to the select line, the trigger cell and the EPROM cell, and a data switching circuit to provide address data to the trigger cell or the EPROM cell. WO2019/009904 discloses a circuit for use with a memory element and a fluid outlet nozzle, the circuit including a data line, a trigger line, and a data line responsive selector for selecting the memory element or the nozzle. BRIEF DESCRIPTION OF THE DRAWINGS [002] Figure 1 is a block diagram illustrating an example of a fluid ejection system. [003] Figure 2 is a schematic diagram illustrating an example of a fluid ejection device. [004] Figure 3 is a block diagram illustrating an example of a circuit including a first memory and a second memory of a fluid ejection device. [005] Figure 4 is a block diagram illustrating another example of a circuit including a first memory and a second memory of a fluid ejection device. [006] Figure 5 is a schematic diagram illustrating an example of a circuit including a memory element of a fluid ejection device. [007] Figure 6 is a schematic diagram illustrating another example of a circuit including a memory element of a fluid ejection device. [008] Figure 7A is a schematic diagram illustrating an example of a circuit including a plurality of memory elements of a fluid ejection device. [009] Figure 7B is a schematic diagram illustrating another example of a circuit including a plurality of memory elements of a fluid ejection device. [010] Figures 8A-8B are schematic diagrams illustrating an example of a circuit including a plurality of memory elements and a plurality of fluid actuation devices of a fluid ejection device. [011] Figure 9A is a schematic diagram illustrating an example of a circuit including a first memory, a second memory, and fluid actuation devices. [012] Figure 9B is a schematic diagram illustrating another example of a circuit including a first memory, a second memory, and fluid actuation devices. [013] Figures 10A and 10B are timing diagrams illustrating an example of the operation of the circuit in Figure 9B. [014] Figures 11A and 11B are timing diagrams illustrating another example of the operation of the circuit in Figure 9B. [015] Figure 12 is a block diagram illustrating an example of a fluid ejection system. [016] Figures 13A-13D are flowcharts illustrating an example of a method for accessing a first memory and a second memory of a fluid ejection device. [017] Figures 14A-14B are flowcharts illustrating an example of a method for accessing a fluid ejection device memory. [018] Figures 15A-15B are flowcharts illustrating another example of a method for accessing a fluid ejection device memory. DETAILED DESCRIPTION [019] In the detailed description that follows, reference is made to the accompanying drawings which form a part hereof, and in which specific examples are shown by way of illustration in which the disclosure can be practiced. It is to be understood that other examples may be used and structural or logical changes may be made without departing from the scope of the present disclosure. The detailed description that follows is therefore not to be considered as limiting, and the scope of the present disclosure is defined by the appended claims. It is to be understood that features of the various examples described in this document may be combined, in part or in whole, with one another, unless specifically noted otherwise. [020] As used in this document, a “logic high” signal is a logic “1” or “on” signal, or a signal having a voltage approximately equal to the logic power supplied to an integrated circuit (for example, between about 1.8 V and 15 V, such as 5.6 V). As used in this document, a “logic low” signal is a logic “0” or “off” signal, or a signal having a voltage approximately equal to a logic power ground return to the logic power supplied to the integrated circuit (for example, about 0 V). [021] A print head for u