BR-112022021777-B1 - METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR DEVICE

BR112022021777B1BR 112022021777 B1BR112022021777 B1BR 112022021777B1BR-112022021777-B1

Abstract

NANOSHEET TRANSISTOR WITH ASYMMETRIC GATE STACK. Resulting methods and structures for nanosheet devices with asymmetric gate stacks are described. A nanosheet stack (102) is formed on a substrate (104). The nanosheet stack (102) includes alternating semiconductor layers (108) and sacrificial layers (110). A sacrificial coating (202) is formed on the nanosheet stack (102) and a dielectric gate structure (204) is formed on the nanosheet stack (102) and the sacrificial coating (202). A first internal spacer (302) is formed on a side wall of the sacrificial layers (110). A gate (112) is formed on channel regions of the nanosheet stack (102). The gate (112) includes a conductive bridge extending over the substrate (104) in a direction orthogonal to the stack of nanosheets (102). A second internal spacer (902) is formed on a side wall of the gate (112). The first internal spacer (302) is formed before the gate stack (112), while the second internal spacer (902) is formed after and, consequently, the gate stack (112) is asymmetric.

Inventors

Ruilong Xie
Carl Radens
Kangguo Cheng
Juntao Li
Dechao Guo
Tao Li
Tsung-Sheng KANG

Assignees

INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date: 20260310
Application Date: 20210430
Priority Date: 20200518

Claims (7)

1. Method for forming a semiconductor device (100), the method characterized in that it comprises: forming (2402) two stacks of nanosheets (102) on a substrate (104), each stack of nanosheets (102) comprising alternating semiconductor layers (108) and sacrificial layers (110); forming (2404) a sacrificial coating (202) on the stacks of nanosheets; forming (2406) a gate dielectric structure (204) comprising a gate dielectric material on the stacks of nanosheets and the sacrificial coating; patterning the stacks of nanosheets, the gate dielectric structure, and the sacrificial coating; forming (2408) a first internal spacer (302) on a first side wall of the sacrificial layers; forming two source and drain regions (402) on the exposed side walls of the semiconductor layers; forming (2410) a gate (112) over channel regions of nanosheet stacks, the gate comprising a conductive bridge extending over the substrate in a direction orthogonal to the nanosheet stack, the conductive bridge centered vertically with respect to the nanosheet stacks, the gate dielectric structure over the gate, wherein the gate formation comprises: forming a gate patterning trench (506) through the gate dielectric structure and through the nanosheet stacks between the two source and drain regions, thereby dividing each nanosheet stack into two portions; removing the sacrificial layers and sacrificial coatings to provide a set of cavities (602); filling the cavities with a gate dielectric and gate material; lower the door material to provide internal cavities (704); form (2412) second internal spacers (902) in the internal cavities on a second side wall of the door; wherein the door dielectric extends between the first internal spacer and the door but not between the second internal spacer and the door; and form an additional source and drain region (904) between two source and drain regions.
2. Method according to claim 1, characterized in that forming the first internal spacer comprises the recess of the sacrificial layers (110).
3. Method according to claim 1, characterized in that forming the gate (112) further comprises: forming a gate dielectric (702); forming a conductive region on the gate dielectric (204); and removing exposed portions of the gate dielectric (204).
4. Method according to claim 1, characterized in that it further comprises forming a gate contact (1004) on a surface of the conducting bridge.
5. Semiconductor device characterized in that it comprises: two stacks of nanosheets (102) on a substrate (104), each stack of nanosheets containing semiconductor layers (108); a gate (112) on the channel regions of the stacks of nanosheets, the gate comprising a conductive bridge extending over the substrate in a direction orthogonal to the stacks of nanosheets, the conductive bridge centered vertically with respect to the stacks of nanosheets; a gate dielectric structure (204) comprising a gate dielectric material over the nanosheet stacks and the gate; a first inner spacer (302) in a first sidewall of the nanosheet stack; two source and drain regions (402) in the sidewalls of the semiconductor layers; second inner spacers (902) in the second sidewalls of the gate; wherein the gate dielectric extends between the first inner spacer and the gate, but not between the second inner spacer and the gate; and an additional source and drain region (904) between the two source and drain regions.
6. Semiconductor device according to claim 5, characterized in that it further comprises a gate contact on a surface of the conductive bridge.
7. Semiconductor device according to claim 6, characterized in that the gate dielectric structure (204) is positioned between the stack of nanosheets (102) and the gate contact.

Description

FUNDAMENTALS [0001] The present invention generally relates to methods of fabrication and resulting structures for semiconductor devices and, more specifically, to an improved process and resulting structures for nanosheet transistors with asymmetric gate stacks. [0002] Known metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication techniques include process flows for constructing planar field-effect transistors (FETs). A planar FET includes a substrate (also known as a silicon wafer); a gate formed on the substrate; source and drain regions formed at opposite ends of the gate; and a channel region near the substrate surface under the gate. The channel region electrically connects the source region to the drain region, while the gate controls the current in the channel. The gate voltage controls whether the drain-to-source path is an open circuit ("off") or a resistive path ("on"). [0003] In recent years, research has been dedicated to the development of non-planar transistor architectures. For example, nanosheet FETs include a non-planar architecture that provides higher device density and some improved performance compared to side-by-side devices. In nanosheet FETs, in contrast to conventional planar FETs, the channel is implemented as a plurality of stacked and spaced nanosheets. The gate stack encompasses the entire perimeter of each nanosheet, thus allowing for more complete depletion in the channel region and also reducing short-channel effects due to more pronounced subthreshold oscillation (SS) and reduced drain-induced barrier (DIBL). SUMMARY [0004] The embodiments of the invention are directed to a method for forming a nanosheet device with stacks of asymmetric gates. A non-limiting example of the method includes forming a stack of nanosheets on a substrate. The stack of nanosheets includes alternating semiconductor layers and sacrificial layers. A sacrificial coating is formed on the stack of nanosheets, and a gate dielectric structure is formed on the stack of nanosheets and the sacrificial coating. A first internal spacer is formed on a side wall of the sacrificial layers. The method includes forming a gate on the channel regions of the stack of nanosheets. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the stack of nanosheets. A second internal spacer is formed on a side wall of the gate. The stack of gates is asymmetric. [0005] The embodiments of the invention are directed to a semiconductor structure. A non-limiting example of the semiconductor structure includes a stack of nanosheets on a substrate and a gate over channel regions of the nanosheet stack. The gate includes a conductive bridge extending over the substrate in a direction orthogonal to the nanosheet stack. A gate dielectric structure is positioned over the nanosheet stack and the gate. A first internal spacer is positioned at one end of the nanosheet stack and a second internal spacer is positioned at a second end of the nanosheet stack. The first internal spacer and the second internal spacer are formed during different parts of the workflow (one before the gate stack and the other after) and, consequently, the gate stack is asymmetrical. A gate dielectric extends between the first internal spacer and the gate, but not between the second internal spacer and the gate. [0006] The embodiments of the invention are directed to a method for forming a nanosheet device with stacks of asymmetric gates. A non-limiting example of the method includes forming a stack of nanosheets on a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A spacer layer is formed on a side wall of the nanosheet stack, and a first gate dielectric structure is formed on the substrate and on a side wall of the spacer layer. The method includes forming a sacrificial coating on the first gate dielectric structure and forming a second gate dielectric structure on the sacrificial coating. The sacrificial layers, the spacer layer, and the sacrificial coating are replaced by a gate. The gate includes a conductive bridge positioned between the first gate dielectric structure and the second gate dielectric structure. [0007] The embodiments of the invention are directed to a semiconductor structure. A non-limiting example of the semiconductor structure includes a stack of nanosheets on a substrate. A first gate dielectric structure is positioned on the substrate. A gate is located over the channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. The conductive bridge is positioned on a surface of the first gate dielectric structure. A second gate dielectric structure is positioned on the conductive bridge. [0008] The embodiments of the invention are directed to a semiconductor structure. A non-limiting example of the semiconductor structure includes a first sta