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CN-111934674-B - Error calibration device and method, phase-locked loop and chip

CN111934674BCN 111934674 BCN111934674 BCN 111934674BCN-111934674-B

Abstract

The application provides an error calibration device, a method, a phase-locked loop and a chip, wherein the device comprises a phase offset controller, an output calibrator and a digital loop filter, wherein the phase offset controller is used for inputting a feedback clock and a preset reference clock output by a DCO at a second moment into a TDC, the output calibrator is used for comparing an actual code output by the TDC with a preset check code and outputting a comparison result to the digital loop filter, the actual code=the unit delay of the phase difference/TDC of the feedback clock output by the DCO at the second moment and the preset reference clock, the check code is obtained by offsetting the feedback clock and/or the preset reference clock output by the DCO at the first moment by the phase offset controller to form a preset phase difference and inputting the reference clock and the feedback clock which form the preset phase difference into the TDC, and the check code=the preset phase difference/unit delay. By comparing the actual code with the check code, the unit delay contained by the two codes can be eliminated, thereby relieving the jitter of the clock output by the DCO.

Inventors

  • GAO LING
  • WANG WENGEN

Assignees

  • 成都海光微电子技术有限公司

Dates

Publication Date
20260508
Application Date
20200820

Claims (14)

  1. 1. An error calibration device, the device comprising: The phase offset controller is used for being connected with the output end of the DCO in the phase-locked loop and the input end of the TDC; an output calibrator coupled to an output of the TDC and an input of a digital loop filter in the phase locked loop; The phase offset controller is used for inputting a feedback clock output by the DCO at the second moment and a preset reference clock into the TDC; the output calibrator is configured to compare an actual code output by the TDC with a preset check code, multiply a compared result with a preset value, so that the multiplied result and the code output by the TDC with a standard unit delay are in the same dimension, and output the multiplied result to the digital loop filter; The actual code=the phase difference between the feedback clock output by the DCO at the second moment and the preset reference clock/the unit delay of the TDC, the check code is obtained by shifting the feedback clock output by the DCO at the first moment and/or the preset reference clock by the phase shift controller to form a preset phase difference and inputting the reference clock and the feedback clock forming the preset phase difference into the TDC, and the check code=the preset phase difference/the unit delay.
  2. 2. The error calibration device of claim 1, wherein, The phase shift controller is used for pre-shifting the feedback clock output by the DCO at the first moment, leading the pre-shifted feedback clock to the preset reference clock for half a clock period, inputting the pre-shifted feedback clock and the preset reference clock into the TDC, and also used for post-shifting the feedback clock output by the DCO at the first moment, leading the post-shifted feedback clock to the preset reference clock for half a clock period, and inputting the post-shifted feedback clock and the preset reference clock into the TDC; The output calibrator is configured to record a first code and a second code of the TDC output, and determine the check code according to the first code and the second code, where the first code=a half clock cycle in front/the unit delay, and the second code=a half clock cycle in back/the unit delay.
  3. 3. The error calibration device of claim 2, wherein the phase offset controller comprises a state machine and a phase offset circuit; the state machine is used for outputting the feedback clock output by the DCO at the first moment and the preset reference clock to the phase shifting circuit, and sending a first instruction to the phase shifting circuit and then sending a second instruction to the phase shifting circuit; The phase shifting circuit is configured to, after receiving a feedback clock output by the DCO at a first time and the preset reference clock, pre-shift the feedback clock output by the DCO at the first time according to the first instruction, input the pre-shifted feedback clock and the preset reference clock to the TDC, post-shift the feedback clock output by the DCO at the first time according to the second instruction, and input the post-shifted feedback clock and the preset reference clock to the TDC; and the state machine is further configured to input a feedback clock output by the DCO at the second moment and the preset reference clock into the TDC.
  4. 4. The error calibration device of claim 1, wherein, The phase offset controller is used for pre-offsetting the feedback clock output by the DCO at the first moment, post-offsetting the preset reference clock, leading the pre-offset feedback clock to be arranged in front of the post-offset reference clock for half a clock period, inputting the pre-offset feedback clock and the post-offset reference clock into the TDC, and also used for post-offsetting the feedback clock output by the DCO at the first moment, leading the preset reference clock, leading the post-offset feedback clock to be arranged behind the pre-offset reference clock for half a clock period, and inputting the post-offset feedback clock and the pre-offset reference clock into the TDC; The output calibrator is configured to record a first code and a second code of the TDC output, and determine the check code according to the first code and the second code, where the first code=a half clock cycle in front/the unit delay, and the second code=a half clock cycle in back/the unit delay.
  5. 5. The error calibration device of claim 1, wherein, The phase offset controller is used for shifting the preset reference clock in a post-shifting way, so that the feedback clock output by the DCO at the first moment is arranged in front of the post-shifting reference clock for half a clock period, and the feedback clock output by the DCO and the post-shifting reference clock are input into the TDC; The output calibrator is configured to record a first code and a second code of the TDC output, and determine the check code according to the first code and the second code, where the first code=a half clock cycle in front/the unit delay, and the second code=a half clock cycle in back/the unit delay.
  6. 6. The error correction device according to any one of claims 2 to 5, characterized in that the output corrector comprises a memory, a subtracter, a divider and a multiplier, the memory being connected to the subtracter and the phase shift controller, respectively, the subtracter being connected to the divider, the memory being further adapted to be connected to the output of the TDC, the divider being adapted to be connected to the output of the TDC, and the multiplier being adapted to be connected to the input of the digital loop filter; The memory is used for storing the first code and the second code, and outputting the first code and the second code to the subtracter based on the control of the phase offset controller; The subtracter is used for subtracting the first code from the second code to obtain the check code and outputting the check code to the divider; The divider is used for dividing the check code and the actual code to obtain a quotient and outputting the quotient to the multiplier; The multiplier is used for multiplying the quotient value with a preset value to obtain the result and outputting the result to the digital loop filter.
  7. 7. A method of error calibration, the method comprising: inputting a feedback clock output by a DCO in a phase-locked loop at a second moment and a preset reference clock into a TDC in the phase-locked loop; comparing the actual code output by the TDC with a preset check code, multiplying the compared result with a preset value to enable the multiplied result and the code output by the TDC in standard unit delay to be in the same dimension, and outputting the multiplied result to a digital loop filter in the phase-locked loop; The actual code=the phase difference between the feedback clock output by the DCO at the second moment and the preset reference clock/the unit delay of the TDC, the check code is obtained by shifting the feedback clock output by the DCO at the first moment and/or the preset reference clock to form a preset phase difference and inputting the reference clock and the feedback clock forming the preset phase difference into the TDC, and the check code=the preset phase difference/the unit delay.
  8. 8. The error correction method of claim 7, wherein the step of determining the check code comprises: The method comprises the steps of outputting a feedback clock by a DCO at a first time, pre-shifting the feedback clock of the DCO at the first time, enabling the pre-shifted feedback clock to be arranged in front of the preset reference clock for half a clock period, inputting the pre-shifted feedback clock and the preset reference clock into the TDC, and post-shifting the feedback clock by the DCO at the first time, enabling the post-shifted feedback clock to be arranged behind the preset reference clock for half a clock period, and inputting the post-shifted feedback clock and the preset reference clock into the TDC; And recording a first code and a second code of the TDC output, and determining the check code according to the first code and the second code, wherein the first code=a half of a front clock cycle/the unit delay, and the second code=a half of a rear clock cycle/the unit delay.
  9. 9. The error correction method of claim 7, wherein the step of determining the check code comprises: Pre-shifting the feedback clock output by the DCO at the first moment, post-shifting the preset reference clock, enabling the pre-shifted feedback clock to be arranged in front of the post-shifted reference clock for half a clock period, and inputting the pre-shifted feedback clock and the post-shifted reference clock into the TDC; and shifting the feedback clock output by the DCO at the first moment in a post-position mode, shifting the preset reference clock in a pre-position mode, enabling the feedback clock with the post-position shift to be placed in a half clock period behind the reference clock with the pre-position shift, and inputting the feedback clock with the post-position shift and the reference clock with the pre-position shift into the TDC; And recording a first code and a second code of the TDC output, and determining the check code according to the first code and the second code, wherein the first code=a half of a front clock cycle/the unit delay, and the second code=a half of a rear clock cycle/the unit delay.
  10. 10. The error correction method of claim 7, wherein the step of determining the check code comprises: The preset reference clock is shifted in a rear mode, so that the feedback clock output by the DCO at the first moment is arranged in front of the reference clock with the shifted in the rear mode for half a clock period, the feedback clock output by the DCO and the reference clock with the shifted in the rear mode are input into the TDC, and the preset reference clock is shifted in a front mode, so that the feedback clock output by the DCO at the first moment is arranged behind the reference clock with the shifted in the front mode for half a clock period, and the feedback clock output by the DCO at the first moment and the reference clock with the shifted in the front mode are input into the TDC; And recording a first code and a second code of the TDC output, and determining the check code according to the first code and the second code, wherein the first code=a half of a front clock cycle/the unit delay, and the second code=a half of a rear clock cycle/the unit delay.
  11. 11. The error correction method according to any one of claims 7 to 10, characterized by comparing an actual code of the TDC output with a preset check code, and outputting a result of the comparison to a digital loop filter in the phase-locked loop, comprising: dividing the check code by the actual code to obtain a quotient; and multiplying the quotient value by a preset value to obtain the result, and outputting the result to the digital loop filter.
  12. 12. The phase-locked loop is characterized by comprising an output calibrator, a DCO, a TDC and a digital loop filter, wherein the output calibrator is connected with the output end of the TDC and the input end of the digital loop filter, the output end of the DCO is connected with the input end of the TDC, and the digital loop filter is connected with the input end of the DCO; the DCO is used for outputting a feedback clock to the TDC at a second moment; the TDC is used for determining an actual code according to the feedback clock and a preset reference clock and outputting the actual code to the output calibrator; The output calibrator is configured to compare the actual code with a preset check code, and multiply the compared result with a preset value, so that the multiplied result is in the same dimension as a code output by a TDC in a standard unit delay, and output the multiplied result to the digital loop filter, where the actual code=a phase difference between a feedback clock output by the DCO at a second time and the preset reference clock/a unit delay of the TDC; The digital loop filter is configured to filter the result and input the result to the DCO to adjust the output of the DCO.
  13. 13. The phase-locked loop of claim 12, further comprising a phase-shift controller coupled to the output of the DCO and the input of the TDC; the phase shift controller is configured to shift the feedback clock output by the DCO at the first time and/or the preset reference clock to form a preset phase difference, and input the reference clock and the feedback clock forming the preset phase difference to the TDC.
  14. 14. A chip comprising a chip core and the phase locked loop of claim 12 or 13 connected to the chip core.

Description

Error calibration device and method, phase-locked loop and chip Technical Field The present application relates to the field of integrated circuits, and in particular, to an error calibration device, an error calibration method, a phase-locked loop, and a chip. Background In a conventional phase locked loop, the phase locked loop generally includes a TDC (Time to Digital Convert, time-to-digital converter), a digital loop filter, a DSM (DELTA SIGMA Modulator), a thermal encoder, a current generator, a DCO (DIGITALLY CONTROLLED OSCILLATOR, digital controlled oscillator), and a frequency divider. The reference clock preset by the phase-locked loop is input to the TDC, the signal output by the frequency divider is also input to the TDC as a feedback clock, and the TDC can determine the phase difference between the feedback clock and the reference clock. Since the TDC is an analog circuit block, the TDC may divide the phase difference by a unit delay of an inverter inside itself to obtain an output code, and output the output code to a digital loop filter for filtering. And the digital loop filter outputs the filtered codes to the DSM and the thermal encoder, respectively. The DSM further filters out and inputs the noise of the denoised fraction in the code to the current generator, and the thermal encoder converts the filtered integer fraction in the code to a thermometer code and inputs it to the current generator as well. The current generator controls the oscillation of the DCO based on the input parameters to adjust the clock output by the DCO. Finally, the clock output after DCO adjustment is divided by a frequency divider and then is input into the TDC as a feedback clock, so that closed-loop adjustment is formed until no phase difference exists between the reference clock and the feedback clock, and phase locking is realized. It will be appreciated that, since the TDC is an analog circuit module, the unit delay of the internal inverter varies with PVT ("P" is "Process", which refers to the Process adopted in the fabrication of the TDC, "V" is "Voltage", which refers to the magnitude of the Voltage applied during the operation of the TDC, "T" is "Temperature", which refers to the Temperature during the operation of the TDC). For example, when the TDC is manufactured by a slow process, the unit delay is larger, resulting in smaller encoding of the TDC output, when the TDC is manufactured by a fast process, the unit delay is smaller, resulting in larger encoding of the TDC output, when the temperature of the TDC is low, the unit delay is larger, resulting in smaller encoding of the TDC output, and when the temperature of the TDC is high, the unit delay is smaller, resulting in larger encoding of the TDC output. The variation of the unit delay causes unstable codes of the TDC output, and the unstable codes further cause significant jitter of the clock of the DCO output after the series of processes. Disclosure of Invention The embodiment of the application aims to provide an error calibration device, an error calibration method, a phase-locked loop and a chip, which are used for realizing that the result output to a digital loop filter is not unstable due to the influence of unit delay change and relieving the jitter of a clock output by a DCO. In a first aspect, an embodiment of the present application provides an error calibration device, which includes a phase offset controller configured to be connected to an output end of a DCO in the phase-locked loop and an input end of a TDC, an output calibrator configured to be connected to an output end of the TDC and an input end of a digital loop filter in the phase-locked loop, the phase offset controller configured to input a feedback clock output by the DCO at a second time and a preset reference clock to the TDC, and output a result of the comparison to the digital loop filter, wherein the actual encoding=a phase difference between the feedback clock output by the DCO at the second time and the preset reference clock/a unit delay of the TDC, the check encoding is to offset the feedback clock output by the DCO at the first time and/or the preset reference clock by the phase offset controller to form a preset phase difference, and to output a result of the phase difference to the digital loop filter, and the actual encoding=the phase difference between the feedback clock output by the DCO at the second time and the preset reference clock/the unit delay. In the embodiment of the application, the output calibrator is preset with the check code equal to the preset phase difference/unit delay, after the output calibrator is put into practical application, when the TDC outputs the practical code equal to the practical phase difference/unit delay, the output calibrator can eliminate the unit delay contained by the practical code and the check code by comparing the practical code with the check code, so that the result output to the digital loop filter is not unstab