CN-112053722-B - Memory device

Abstract

There is provided a memory device including a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of word lines extending in a first direction and stacked in a second direction substantially perpendicular to the first direction, and a plurality of transfer transistors disposed in the first semiconductor layer, wherein a first transfer transistor of the plurality of transfer transistors is disposed between a first signal line of the plurality of signal lines and a first word line of the plurality of word lines, and wherein the plurality of signal lines and a common source line are disposed at the same level.

Inventors

• Yin Jinghe
• JIN CANGAO
• Guo Panshuo

Assignees

• 三星电子株式会社

Dates

Publication Date

20260505

Application Date

20200120

Priority Date

20190605

Claims (19)

1. 1. A memory device, the memory device comprising: A memory cell array disposed in the first semiconductor layer, the memory cell array including a plurality of word lines extending in a first direction and stacked in a second direction perpendicular to the first direction, and A plurality of transfer transistors disposed in the first semiconductor layer, wherein a first transfer transistor of the plurality of transfer transistors is disposed between a first signal line of the plurality of signal lines and a first word line of the plurality of word lines, Wherein the plurality of signal lines are arranged at the same level as the common source line, an Wherein the memory device is a non-volatile memory device, Wherein the memory device further comprises a gate extending in a first direction between the plurality of signal lines and the plurality of word lines, wherein the first pass transistor comprises a channel extending from the first signal line through the gate in a second direction, Wherein the memory cell array further includes a plurality of channel structures extending from the common source line in the second direction through the ground select line, an Wherein a first channel structure of the plurality of channel structures has a first width in a region between the ground select line and the first word line, and a channel of the first pass transistor has a second width in a region between the gate and the first word line, the second width being greater than the first width.
2. 2. The memory device of claim 1, wherein the first pass transistor is a vertical pass transistor, and Wherein each of the plurality of pass transistors includes a vertical channel, wherein a top of the plurality of vertical channels is below the first word line.
3. 3. The memory device of claim 2, wherein a width of the channel between the gate and the first word line is greater than a width of the channel under the gate.
4. 4. The memory device of claim 3, wherein tops of the plurality of vertical channels are at a same level as each other, and Wherein the second width is at least twice the first width.
5. 5. The memory device according to claim 1, wherein the plurality of transfer transistors are formed in a region of the plurality of word lines forming a stair shape.
6. 6. The memory device of claim 1, further comprising a second semiconductor layer, wherein the first semiconductor layer is stacked on the second semiconductor layer in a second direction, the second semiconductor layer comprises a second transistor electrically connected to the first transfer transistor, and Wherein the second transistor is included in the row decoder.
7. 7. The memory device of claim 1, wherein a gate is connected to at least one of the plurality of pass transistors, wherein the gate is disposed at a same level as a ground select line.
8. 8. The memory device according to claim 1, wherein the plurality of transfer transistors are commonly connected to a gate line, and Wherein the plurality of pass transistors are provided with the same block select signal.
9. 9. A memory device, the memory device comprising: a memory cell array including a plurality of word lines stacked in a vertical direction, and A plurality of vertical transfer transistors, wherein a first vertical transfer transistor of the plurality of vertical transfer transistors includes a first vertical channel extending in a vertical direction between a first driving signal line and a first word line of the plurality of word lines, wherein the first vertical channel is disposed near an end of the first word line, and Wherein the first driving signal line and the common source line are arranged in the same layer, Wherein the memory device further comprises a gate electrode disposed between the first driving signal line and the first word line, wherein a first vertical channel of the first vertical transfer transistor extends from the first driving signal line in a vertical direction through the gate electrode, Wherein the memory cell array further includes a plurality of channel structures extending from the common source line in a vertical direction through the ground select line, an Wherein a first channel structure of the plurality of channel structures has a first width in a region between the ground select line and the first word line, and a first vertical channel of the first vertical transfer transistor has a second width in a region between the gate and the first word line, the second width being greater than the first width.
10. 10. The memory device according to claim 9, wherein a first driving signal line is provided on a base layer of the first semiconductor layer and extends horizontally, the first driving signal line is connected to a transistor included in the second semiconductor layer, and Wherein the first driving signal line is connected to the transistor in the second semiconductor layer through the contact and the metal pattern in the first semiconductor layer.
11. 11. The memory device according to claim 9, wherein the plurality of vertical transfer transistors includes a second vertical transfer transistor including a second vertical channel extending in a vertical direction between a second driving signal line and a second word line of the plurality of word lines, the second vertical channel being disposed near an end of the second word line.
12. 12. The memory device of claim 11, wherein the end of the second word line is closer to a cell region of the memory cell array than the end of the first word line, Wherein the first vertical channel and the second vertical channel have the same height as each other in the vertical direction, an Wherein a top surface of the first vertical channel and a top surface of the second vertical channel are located below a bottom surface of the first word line.
13. 13. The memory device of claim 9, wherein the first word line comprises a tungsten region and a nitride region, and Wherein the tungsten region is connected to the contact and the contact is connected to the first word line through the tungsten region.
14. 14. The memory device of claim 9, the memory device further comprising: A ground selection line disposed between the common source line and the first word line, wherein the gate and the ground selection line are disposed at the same level as each other, an Wherein the memory cell array and the plurality of vertical transfer transistors are disposed in a first semiconductor layer, and at least a portion of the row decoder is disposed in a second semiconductor layer below the first semiconductor layer.
15. 15. The memory device according to claim 9, wherein a first word line connected to the first driving signal line is supplied with a program voltage, and a second word line connected to the second driving signal line is supplied with a pass voltage, and Wherein the programming voltage is 10V to 25V and the pass voltage is 5V to 15V.
16. 16. The memory device according to claim 9, wherein a first word line connected to the first driving signal line is supplied with a read voltage, and a second word line connected to the second driving signal line is supplied with a read pass voltage, and Wherein the read voltage is-1V to 10V, and the read pass voltage is 4V to 10V.
17. 17. The memory device according to claim 9, wherein a first word line connected to the first driving signal line is supplied with an erase voltage, and Wherein the erase voltage is-2V to 3V.
18. 18. A memory device, the memory device comprising: A first semiconductor layer including a memory cell array including a plurality of word lines stacked in a vertical direction, a plurality of transfer transistors, a first transfer transistor of the plurality of transfer transistors being connected to a driving signal line, and a gate electrode arranged on the same layer as a ground selection line, and A second semiconductor layer including a first transistor connected to a contact, the contact being connected to a second bond pad, the second bond pad being connected to the first bond pad, Wherein the first pass transistor is connected to the gate, the gate is connected to the contact, the contact is connected to the first bond pad, and The plurality of word lines have a stepped shape in a region where the first pass transistor is placed, Wherein the first transfer transistor includes a channel extending from the driving signal line in a vertical direction through the gate electrode, and the first transfer transistor is disposed between the driving signal line and a first word line of the plurality of word lines, Wherein the memory cell array further includes a plurality of channel structures extending from the common source line in a vertical direction through the ground select line, an Wherein a first channel structure of the plurality of channel structures has a first width in a region between the ground select line and the first word line, and a channel of the first pass transistor has a second width in a region between the gate and the first word line, the second width being greater than the first width.
19. 19. The memory device of claim 18, wherein the second semiconductor layer is bonded to the first semiconductor layer, and Wherein the second semiconductor layer includes a transistor connected to a gate electrode in the first semiconductor layer.

Description

Memory device The present application claims priority from korean patent application No. 10-2019-0066996 filed in the korean intellectual property office on 5 th month 6 of 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field The inventive concept relates to a memory device, and more particularly, to a nonvolatile memory device having a peripheral on cell (cell over periphery, COP) structure. Background As information communication apparatuses become more multifunctional, highly integrated and high-capacity memory devices are required. As the size of memory cells is reduced to increase the integration of memory devices, the operating circuitry and/or wiring structures of memory devices have become complex. Accordingly, techniques for designing highly integrated memory devices having excellent electrical characteristics are being developed. In particular, in order to increase the integration of the memory device, the number of word lines stacked on the substrate in the vertical direction may be increased. However, in this case, the number of transfer transistors connected to the word line increases, and thus the chip size increases. Disclosure of Invention According to an exemplary embodiment of the inventive concept, there is provided a memory device including a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of word lines extending in a first direction and stacked in a second direction substantially perpendicular to the first direction, and a plurality of transfer transistors disposed in the first semiconductor layer, wherein a first transfer transistor of the plurality of transfer transistors is disposed between a first signal line of the plurality of signal lines and a first word line of the plurality of word lines, wherein the plurality of signal lines and a common source line are disposed at a same level. According to an exemplary embodiment of the inventive concept, there is provided a memory device including a memory cell array including a plurality of word lines stacked in a vertical direction, and a plurality of vertical transfer transistors, wherein a first vertical transfer transistor of the plurality of vertical transfer transistors includes a first vertical channel extending in the vertical direction between a first driving signal line and a first word line of the plurality of word lines, wherein the first vertical channel is disposed near an end of the first word line, and wherein the first driving signal line and a common source line are arranged in the same layer. According to an exemplary embodiment of the inventive concept, there is provided a memory device including a first semiconductor layer including a memory cell array including a plurality of word lines stacked in a vertical direction, and a plurality of transfer transistors, a first transfer transistor of the plurality of transfer transistors being connected to a driving signal line, wherein the driving signal line is connected to a gate electrode arranged on the same layer as a ground selection line. Drawings The above and other features of the inventive concept will be more clearly understood by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: Fig. 1 is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept; Fig. 2 illustrates a structure of a memory device according to an exemplary embodiment of the inventive concept; fig. 3 illustrates a memory cell array according to an exemplary embodiment of the inventive concept; Fig. 4 illustrates an equivalent circuit of a memory block according to an exemplary embodiment of the inventive concept; Fig. 5 illustrates a row decoder and pass transistor circuit according to an exemplary embodiment of the inventive concept; fig. 6 is a cross-sectional view illustrating a memory device including the pass transistor circuit of fig. 5 according to an exemplary embodiment of the inventive concept; fig. 7 is a cross-sectional view illustrating a memory device including the pass transistor circuit of fig. 5 according to an exemplary embodiment of the inventive concept; fig. 8 illustrates a row decoder and pass transistor circuit according to an exemplary embodiment of the inventive concept; Fig. 9 is a cross-sectional view illustrating a memory device including the pass transistor circuit of fig. 8 according to an exemplary embodiment of the inventive concept; Fig. 10 is a top view illustrating a memory device including the pass transistor circuit of fig. 5 according to an exemplary embodiment of the inventive concept; fig. 11 is a cross-sectional view taken along line XI-XI' of fig. 10 according to an exemplary embodiment of the inventive concept; fig. 12 is a cross-sectional view illustrating a memory device including the pass transistor circuit of fig. 5 according to an exemplary embodiment of th