CN-112071895-B - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Abstract

A semiconductor device is provided, the semiconductor device including an active region on a substrate and including first and second sidewalls extending in a first direction, and an epitaxial pattern on the active region, wherein the epitaxial pattern includes first and second epitaxial sidewalls extending from the first and second sidewalls, respectively, the first epitaxial sidewall includes a first epitaxial lower sidewall, a first epitaxial upper sidewall, and a first epitaxial connection sidewall connecting the first epitaxial lower sidewall and the first epitaxial upper sidewall, the second epitaxial sidewall includes a second epitaxial lower sidewall, a second epitaxial upper sidewall, and a second epitaxial connection sidewall connecting the second epitaxial lower sidewall and the second epitaxial upper sidewall, a distance between the first and second epitaxial upper sidewalls decreases as it is away from the active region, and the first and second epitaxial lower sidewalls extend parallel to a top surface of the substrate.

Inventors

• Liang Zhengji
• SONG SHENGMIN
• ZHENG XIUZHEN
• Pei Dongyi
• XU FENGXI

Assignees

• 三星电子株式会社

Dates

Publication Date

20260512

Application Date

20200608

Priority Date

20190610

Claims (7)

1. 1. A semiconductor device, comprising: a first active region disposed in the first region of the substrate and including a first sidewall and a second sidewall extending in a first direction; a second active region disposed in the second region of the substrate and including third and fourth sidewalls extending in a second direction; a first epitaxial pattern disposed on the first active region, and A second epitaxial pattern disposed on the second active region, Wherein the first epitaxial pattern includes first and second epitaxial sidewalls extending from the first and second sidewalls of the first active region, respectively, Wherein the first epitaxial side wall comprises a first epitaxial lower side wall, a first epitaxial upper side wall and a first epitaxial connecting side wall connecting the first epitaxial lower side wall and the first epitaxial upper side wall, Wherein the second epitaxial side wall comprises a second epitaxial lower side wall, a second epitaxial upper side wall and a second epitaxial connecting side wall connecting the second epitaxial lower side wall and the second epitaxial upper side wall, Wherein the second epitaxial pattern includes a third epitaxial sidewall and a fourth epitaxial sidewall extending from the third sidewall and the fourth sidewall of the second active region, respectively, Wherein the third epitaxial sidewall comprises a third epitaxial lower sidewall and a third epitaxial upper sidewall directly connected to the third epitaxial lower sidewall, Wherein the fourth epitaxial sidewall comprises a fourth epitaxial lower sidewall and a fourth epitaxial upper sidewall directly connected to the fourth epitaxial lower sidewall, Wherein the first to fourth upper epitaxial sidewalls and the third and fourth lower epitaxial sidewalls are formed of crystal planes included in a first crystal plane group, and Wherein at least a portion of the first epitaxial lower sidewall and at least a portion of the second epitaxial lower sidewall are formed of crystal planes included in a second crystal plane family, Wherein the first crystal plane group is a {111} crystal plane group, Wherein the second crystal plane group is one of a {111} crystal plane group and a {100} crystal plane group, Wherein the first region and the second region are P-type metal oxide semiconductor regions.
2. 2. The semiconductor device of claim 1, wherein the first and second epitaxial connection sidewalls are formed of crystal planes included in a third crystal plane group that is different from the first and second crystal plane groups.
3. 3. The semiconductor device according to claim 1, wherein a width of the first active region in a third direction intersecting the first direction is larger than a width of the second active region in a fourth direction intersecting the second direction.
4. 4. The semiconductor device according to claim 1, Wherein a distance between the first epitaxial sidewall and the second epitaxial sidewall in a third direction intersecting the first direction decreases as a distance from the first active region increases in a fourth direction perpendicular to the first direction and the third direction, and Wherein a distance between the third epitaxial sidewall and the fourth epitaxial sidewall in a fifth direction intersecting the second direction decreases as a distance from the second active region increases in a sixth direction perpendicular to the second direction and the fifth direction.
5. 5. The semiconductor device of claim 4, wherein each of the first and second epitaxial lower sidewalls is parallel to a top surface of the substrate.
6. 6. The semiconductor device of claim 1, wherein the first active region comprises a planar top surface connecting the first sidewall and the second sidewall.
7. 7. The semiconductor device according to claim 1, Wherein the first epitaxial connection sidewall and the second epitaxial connection sidewall are formed of crystal planes included in a third family of crystal planes, and Wherein the third family of crystal planes is the {110} family of crystal planes.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Cross Reference to Related Applications The present application claims priority from korean patent application No.10-2019-0067746 filed on the korean intellectual property office on 10 th month 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field The present inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device having a gate-all-around structure. Background As a scaling technique for increasing the density of a semiconductor device, a gate-around structure in which nanowire-type silicon bodies are formed on a substrate and gates are formed around the silicon bodies has been proposed. Since the gate-all-around structure uses a three-dimensional (3D) channel, it can be scaled conveniently. In addition, the current control capability can be improved without increasing the gate length. In addition, a Short Channel Effect (SCE), a phenomenon in which the potential of a channel region is affected by a drain voltage, can be effectively suppressed. Disclosure of Invention Embodiments of the inventive concept provide a semiconductor device capable of improving performance and reliability by controlling a shape of an epitaxial pattern in a transistor having a gate-all-around structure. However, embodiments of the inventive concept are not limited to those set forth herein. The above and other embodiments of the inventive concept will become more apparent to those of ordinary skill in the art to which the inventive concept pertains by referencing the detailed description of the inventive concept given below. According to an example of the inventive concept, the present disclosure relates to a semiconductor device including an active region disposed on a substrate and including first and second sidewalls extending in a first direction, and an epitaxial pattern disposed on the active region, wherein the epitaxial pattern includes first and second epitaxial sidewalls extending from the first and second sidewalls of the active region, respectively, wherein the first epitaxial sidewall includes a first epitaxial lower sidewall, a first epitaxial upper sidewall, and a first epitaxial connection sidewall connecting the first epitaxial lower sidewall and the first epitaxial upper sidewall, wherein the second epitaxial sidewall includes a second epitaxial lower sidewall, a second epitaxial upper sidewall, and a second epitaxial connection sidewall connecting the second epitaxial lower sidewall and the second epitaxial upper sidewall, wherein a distance between the first epitaxial upper sidewall and the second epitaxial upper sidewall in a second direction perpendicular to the first direction increases with a distance from the active region in a third direction perpendicular to the first and second direction, and wherein the first lower sidewall and the second epitaxial lower sidewall extend parallel to a top surface of the substrate. According to an example of the inventive concept, the present disclosure relates to a semiconductor device including an active region including first and second sidewalls extending in a first direction, and an epitaxial pattern disposed on the active region, wherein the epitaxial pattern includes first and second epitaxial sidewalls extending from the first and second sidewalls of the active region, respectively, wherein the first epitaxial sidewall includes a first epitaxial lower sidewall, a first epitaxial upper sidewall, and a first epitaxial connection sidewall connecting the first epitaxial lower sidewall and the first epitaxial upper sidewall, wherein the second epitaxial sidewall includes a second epitaxial lower sidewall, a second epitaxial upper sidewall, and a second epitaxial connection sidewall connecting the second epitaxial lower sidewall and the second epitaxial upper sidewall, wherein the first and second epitaxial upper sidewalls are formed of crystal planes included in a first crystal plane group, and wherein the first and second epitaxial connection sidewalls are formed of crystal planes included in a second crystal plane group different from the first crystal plane group. According to an example of the inventive concept, the present disclosure relates to a semiconductor device including a first active region disposed in a first region of a substrate and including a first sidewall and a second sidewall extending in a first direction, a second active region disposed in a second region of the substrate and including a third sidewall and a fourth sidewall extending in a second direction, a first epitaxial pattern disposed on the first active region, and a second epitaxial pattern disposed on the second active region, wherein the first epitaxial pattern includes a first epitaxial sidewall and a second epitaxial sidewall extending from the first sidewall and the second sidewall of the active region, r