CN-112309475-B - Nonvolatile memory device and method of controlling initialization thereof

Abstract

The present invention relates to a nonvolatile memory device and an initialization method for controlling the same. A method includes performing a first sensing operation to sense write setup data stored in a first memory cell of a first memory plane and store first read setup data in a first page buffer circuit of the first memory plane, performing a second sensing operation to sense write setup data stored in a second memory cell of a second memory plane and store second read setup data in a second page buffer circuit of the second memory plane, and performing a dump operation to store recovery setup data corresponding to the write setup data in a buffer based on the first read setup data and the second read setup data.

Inventors

• SHEN ZHIYUAN
• Nan Shangwan
• Pu Xiangyuan

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20200612

Priority Date

20190731

Claims (20)

1. 1. A method of controlling initialization of a non-volatile memory device, comprising: Performing a first sensing operation to sense write setting data stored in a first memory cell of a first memory plane of the nonvolatile memory device and store the first read setting data in a first page buffer circuit of the first memory plane; Performing a second sensing operation to sense write setup data stored in a second memory cell of a second memory plane of the non-volatile memory device and store second read setup data in a second page buffer circuit of the second memory plane, and A dump operation is performed to store recovery setting data corresponding to the write setting data in a buffer of the nonvolatile memory device based on the validity of the first read setting data and the validity of the second read setting data.
2. 2. The method of claim 1, wherein performing a dump operation comprises: verifying validity of the first read setting data using a first verification circuit connected to the first page buffer circuit; verifying validity of the second read setup data using a second verification circuit connected to the second page buffer circuit, and Based on the validity verification result of the first read setting data and the validity verification result of the second read setting data, valid data corresponding to one of the first data unit and the second data unit is stored in the buffer.
3. 3. The method of claim 2, wherein verifying the validity of the first read setup data comprises: Verifying validity of each of a plurality of first data units corresponding to first read setting data divided by a unit number of bits, and Wherein verifying the validity of the second read setup data comprises: validity of each of a plurality of second data units corresponding to second read setting data divided by a unit number of bits is verified.
4. 4. The method of claim 3, wherein storing valid data comprises: sequentially storing first valid data units in a buffer based on the first data units before one of the plurality of first data units is determined to be an invalid data unit, and Starting from a second data unit corresponding to the first data unit determined as an invalid data unit, the second valid data units are sequentially stored in the buffer based on the second data unit.
5. 5. The method of claim 4, wherein the first verification circuitry is enabled to verify the validity of the first data unit and the second verification circuitry is disabled before the one of the plurality of first data units is determined to be an invalid data unit, and wherein the first verification circuitry is disabled and the second verification circuitry is enabled to verify the validity of the second data unit after the one of the plurality of first data units is determined to be an invalid data unit.
6. 6. The method of claim 4, wherein when the second sensing operation is not completed at a point in time when the one of the plurality of first data units is determined to be an invalid data unit, both the first and second verification circuits are disabled until the second sensing operation is completed.
7. 7. The method of claim 4, wherein storing valid data further comprises: Sequentially storing second valid data units in a buffer based on the second data units before one of the plurality of second data units is determined to be an invalid data unit, and Starting from a first data unit corresponding to a second data unit determined as an invalid data unit, the first valid data units are sequentially stored in a buffer based on the first data unit.
8. 8. The method of claim 3, wherein storing valid data comprises: sequentially storing the first valid data units based on the first data units determined to be valid data units, and The second valid data units are sequentially stored based on the second data units corresponding to the first data units determined to be invalid data units.
9. 9. The method of claim 8, wherein the first verification circuitry and the second verification circuitry are enabled simultaneously such that a dump operation with respect to the first valid data unit and a dump operation with respect to the second valid data unit are performed alternatively.
10. 10. The method of claim 8, wherein first verification circuitry is enabled first and second verification circuitry is enabled after disabling the first verification circuitry such that a dump operation is performed with respect to a second valid data unit after a dump operation is completed with respect to a first valid data unit.
11. 11. The method of claim 1, wherein the first and second sensing operations begin simultaneously such that the first and second sensing operations complete simultaneously.
12. 12. The method of claim 1, wherein the first sensing operation starts in advance of the start of the second sensing operation such that a completion time point of the first sensing operation precedes a completion time point of the second sensing operation.
13. 13. The method of claim 1, wherein the dumping operation begins at a completion time point of the second sensing operation.
14. 14. The method of claim 1, wherein the dumping operation begins at a completion time point of the first sensing operation.
15. 15. The method of claim 1, further comprising: Performing a third sensing operation to sense write setup data stored in a third memory cell of the first memory plane and store the third read setup data in a first page buffer circuit of the first memory plane when a dump operation based on the first read setup data and the second read setup data is determined to fail; When a dump operation based on the first read setting data and the second read setting data is determined to fail, performing a fourth sensing operation to sense write setting data stored in a fourth memory cell of the second memory plane and store the fourth read setting data in a second page buffer circuit of the second memory plane, and A dump operation is performed to store recovery setting data corresponding to the write setting data in the buffer based on the third read setting data and the fourth read setting data.
16. 16. The method of claim 1, further comprising: When a dump operation based on the first read setting data and the second read setting data is determined to fail, performing a third sensing operation to sense write setting data stored in a third memory cell of a third memory plane and store the third read setting data in a third page buffer circuit of the third memory plane, and A dump operation is performed to store recovery setting data corresponding to the write setting data in the buffer based on the first, second, and third read setting data.
17. 17. The method of claim 2, wherein the write setting data is obtained by copying each bit of the original setting data into a plurality of copy bits, and Wherein each of the first verification circuit and the second verification circuit includes a majority voter circuit configured to determine whether a number of bits of equal value among the plurality of replica bits is equal to or greater than a reference number.
18. 18. A method of controlling initialization of a non-volatile memory device, comprising: Performing a first sensing operation to sense write setting data stored in a first memory cell of a first memory plane of the nonvolatile memory device and store the first read setting data in a first page buffer circuit of the first memory plane; Performing a second sensing operation to sense write setup data stored in a second memory cell of a second memory plane of the non-volatile memory device and store second read setup data in a second page buffer circuit of the second memory plane; Verifying validity of each of a plurality of first data units corresponding to first read setting data divided by a unit number of bits using a first verification circuit connected to a first page buffer circuit; Verifying validity of each of a plurality of second data units corresponding to second read setup data divided by a unit number of bits using a second verification circuit connected to the second page buffer circuit; Selectively enabling a first verification circuit and a second verification circuit based on a validity verification result for each of the plurality of first data units and a validity verification result for each of the plurality of second data units, and Based on the validity verification result for each of the plurality of first data units and the validity verification result for each of the plurality of second data units, storing a valid data unit corresponding to one of the first data unit and the second data unit in a buffer of the nonvolatile memory device.
19. 19. A non-volatile memory device, comprising: a first memory plane including a first memory cell storing write setting data and a first page buffer circuit storing first read setting data sensed from the first memory cell; A second memory plane including a second memory cell storing write setup data and a second page buffer circuit storing second read setup data sensed from the second memory cell; a first verification circuit connected to the first page buffer circuit, the first verification circuit configured to verify validity of the first read setting data; a second verification circuit connected to the second page buffer circuit, the second verification circuit configured to verify validity of the second read setup data; dump control logic configured to determine valid data corresponding to one of the first read setup data and the second read setup data based on a result of the validity verification of the first read setup data and a result of the validity verification of the second read setup data, and A buffer configured to store valid data provided from the dump control logic.
20. 20. The non-volatile memory device of claim 19, wherein the non-volatile memory device is a vertical NAND flash memory device such that each of the first and second memory planes includes NAND flash memory cells stacked in a vertical direction to form a cell string.

Description

Nonvolatile memory device and method of controlling initialization thereof Cross Reference to Related Applications The present application claims priority from korean patent application No. 10-2019-0092925 filed in the Korean Intellectual Property Office (KIPO) on 7.31 of 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field Example embodiments relate generally to semiconductor integrated circuits, and more particularly, to a nonvolatile memory device and a method of controlling initialization of the nonvolatile memory device. Background Nonvolatile memory devices, such as flash memory devices, resistive memory devices, and the like, may store data by programming each memory cell (memory cell) to have one of a threshold voltage distribution or a resistance distribution corresponding to a different logic state. Initialization of the non-volatile memory device may include the process of moving stored setup data from the non-volatile memory device to another memory component. Three-dimensional nonvolatile memory devices, such as vertical NAND flash memory devices, have been developed to increase the degree of integration of memory cells. As the integration level and memory capacity of the nonvolatile memory device increase, the time for initializing the nonvolatile memory device increases. Disclosure of Invention An aspect provides a nonvolatile memory device and a method of controlling initialization of the nonvolatile memory device, which can efficiently perform the initialization. According to an aspect of one or more example embodiments, there is provided a method including performing a first sensing operation to sense write setup data stored in a first memory cell of a first memory plane and store the first read setup data in a first page buffer circuit of the first memory plane, performing a second sensing operation to sense write setup data stored in a second memory cell of a second memory plane and store the second read setup data in a second page buffer circuit of the second memory plane, and performing a dump (dump-down) operation to store recovery setup data corresponding to the write setup data in a buffer based on the first read setup data and the second read setup data. According to another aspect of one or more example embodiments, a method is provided that includes performing a first sensing operation to sense write set data stored in first memory cells of a first memory plane and store the first read set data in first page buffer circuitry of the first memory plane, performing a second sensing operation to sense write set data stored in second memory cells of a second memory plane and store the second read set data in second page buffer circuitry of the second memory plane, verifying validity of each of a plurality of first data cells (data units) corresponding to the first read set data divided by unit bit number using first verification circuitry connected to the first page buffer circuitry, verifying validity of each of a plurality of second data cells corresponding to the second read set data divided by unit bit number using second verification circuitry connected to the second page buffer circuitry, verifying validity of each of the plurality of second data cells based on the second set data cells divided by unit bit number, and on a result of the first verification circuitry and the validity of each of the plurality of second data cells and the second data buffer circuitry, and verifying validity of each of the plurality of second data cells based on the first data cells and the second data unit and the second verification result. According to yet another aspect of one or more example embodiments, there is provided a non-volatile memory device including a first memory plane including a first memory cell storing write setup data and a first page buffer circuit storing first read setup data sensed from the first memory cell, a second memory plane including a second memory cell storing write setup data and a second page buffer circuit storing second read setup data sensed from the second memory cell, a first verification circuit connected to the first page buffer circuit, the first verification circuit configured to verify validity of the first read setup data, a second verification circuit connected to the second page buffer circuit, the second verification circuit configured to verify validity of the second read setup data, dump control logic configured to determine valid data corresponding to one of the first read setup data and the first read setup data based on a validity verification result of the first read setup data and a validity verification result of the second read setup data, and a buffer configured to store dump logic provided with valid data from the control logic. Drawings Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanyin