CN-112398444-B - Integrated multi-path power amplifier with interdigital transistors

CN112398444BCN 112398444 BCN112398444 BCN 112398444BCN-112398444-B

Abstract

A multi-path amplifier (e.g., a doherty amplifier) includes first and second amplifier inputs and an amplifier output integrally formed with a semiconductor die, and at least two amplifier units positioned adjacent to each other between the amplifier inputs and the amplifier outputs. Each amplifier cell includes a first transistor and a second transistor integrally formed with a semiconductor die, where the first transistor and the second transistor each include a transistor input and a transistor output. The first transistor input is coupled to the first amplifier input and the second transistor input is coupled to the second amplifier input. The combining node is coupled to the second transistor output and to the amplifier output, and the first phase shifting element is electrically connected between the first transistor output and the combining node.

Inventors

IBRAHIM KHALIL
Hussein Hosanna radhani
HUMAYUN KABIR

Assignees

恩智浦美国有限公司
恩智浦美国有限公司

Dates

Publication Date: 20260421
Application Date: 20200810
Priority Date: 20190815

Claims (9)

1. A multi-path amplifier, comprising: a semiconductor die; A first input signal manifold positioned at an input side of the semiconductor die and integrally formed with the semiconductor die, wherein the first input signal manifold is coupled to a first amplifier input; A second input signal manifold positioned at the input side of the semiconductor die and integrally formed with the semiconductor die, wherein the second input signal manifold is coupled to a second amplifier input; An output signal manifold positioned at an output side of the semiconductor die and integrally formed therewith, wherein the output signal manifold is coupled to an amplifier output, and At least two amplifier units positioned between the input side and the output side of the semiconductor die, wherein the at least two amplifier units are positioned adjacent to each other, and each of the at least two amplifier units comprises: a first transistor integrally formed with the semiconductor die, wherein the first transistor has a first transistor input and a first transistor output, wherein the first transistor input is coupled to the first amplifier input; A second transistor integrally formed with the semiconductor die, wherein the second transistor has a second transistor input and a second transistor output, wherein the second transistor input is coupled to the second amplifier input; A combining node coupled to the second transistor output and to the amplifier output, and A first phase shifting element electrically connected between the first transistor output and the combining node.
2. The multi-path amplifier of claim 1, wherein the first phase shifting element comprises: a first inductor, wherein a first end of the first inductor is coupled to the first transistor output and a second end of the first inductor is coupled to the combining node.
3. The multi-path amplifier of claim 2, wherein the first inductor is a spiral inductor integrally formed with the semiconductor die.
4. The multi-path amplifier of claim 2, wherein the first inductor is a discrete inductor coupled to a top surface of the semiconductor die.
5. The multi-path amplifier of claim 2, wherein the first inductor has an inductance value in the range of 0.1 nanohenries to 20 nanohenries.
6. The multi-path amplifier of claim 2, wherein: The first transistor is a first field effect transistor comprising a first drain region, a first source region, and a first gate terminal, wherein a first drain-source capacitance exists between the first drain region and the first source region, the first gate terminal is coupled to the first transistor input, and the first drain region is coupled to the first transistor output; The second transistor is a second field effect transistor comprising a second drain region, a second source region, and a second gate terminal, wherein a second drain-source capacitance exists between the second drain region and the second source region, the second gate terminal is coupled to the second transistor input, and the second drain region is coupled to the second transistor output, and Wherein the first drain-source capacitance, the second drain-source capacitance, and the first inductor cause a 90 degree phase delay to be imparted to a radio frequency signal communicated between the first drain region and the combining node.
7. The multi-path amplifier of claim 1, wherein: The first transistor is a first field effect transistor comprising a first transistor finger comprising an elongated first drain region, an elongated first source region, and an elongated first gate terminal, wherein the first gate terminal is coupled to the first transistor input and the first drain region is coupled to the first transistor output, and The second transistor is a second field effect transistor comprising a second transistor finger comprising an elongated second drain region, an elongated second source region, and an elongated second gate terminal, wherein the second gate terminal is coupled to the second transistor input and the second drain region is coupled to the second transistor output.
8. The multi-path amplifier of claim 7, wherein the first length of the first transistor finger is shorter than the second length of the second transistor finger.
9. The multi-path amplifier of claim 8, wherein the first and second transistor fingers have input ends aligned along a first line perpendicular to the first and second lengths of the first and second transistor fingers, the second transistor finger has an output end aligned along a second line perpendicular to the first and second lengths of the first and second transistor fingers, and the first phase shifting element is positioned between the output end of the first and second transistor fingers.

Description

Integrated multi-path power amplifier with interdigital transistors Technical Field Embodiments of the subject matter described herein relate generally to power amplifiers having multiple sub-amplifiers, and more particularly to doherty power amplifiers having carrier and peaking amplifiers and output combining circuits. Background Doherty power amplifiers have been one of the most popular amplifiers for cellular infrastructure applications for many years. The bi-directional doherty amplifier comprises two sub-amplifiers (i.e. a carrier amplifier and a peaking amplifier) connected in parallel between an amplifier input and an amplifier output. During operation, an input Radio Frequency (RF) signal is split into a carrier signal and a peaking signal, and a 90 degree phase difference is applied between the carrier signal and the peaking signal before being amplified by the carrier amplifier and the peaking amplifier. On the output side, one of the amplified carrier signal or peaking signal is then transmitted over an n×90 degree transmission line (n=1, 2..) while the other of the amplified carrier signal or peaking signal is transmitted over an (n-1) ×90 degree transmission line, and the amplified signals are then combined together by a signal combiner. This makes it possible for the active load pulling of the carrier amplifier and the peaking amplifier. In some typical doherty amplifier configurations, the carrier amplifier and peaking amplifier are implemented on two different semiconductor die (i.e., one die for the carrier amplifier and the other die for the peaking amplifier) mounted to a package substrate or Printed Circuit Board (PCB). For example, each of the carrier amplifier and peaking amplifier may be implemented using multi-finger field effect transistors, and within each die, the amplified signals generated by each transistor finger are combined at the output bond pad. Wire bond arrays are commonly used to transfer amplified carrier signals and peaking signals from output bond pads to output leads or to conductive structures on a package substrate or PCB. In a 90-0 doherty amplifier configuration, the amplified carrier signal or amplified peaking signal is conducted through a conductor (e.g., transmission line) of electrical length 90 degrees (e.g., quarter wavelength transmission line) prior to combining the signals. Similarly, in a 90-180 doherty amplifier configuration, prior to combining the signals, the amplified carrier signal or amplified peaking signal is conducted through a transmission line having an electrical length of 90 degrees, and the other of the amplified carrier signal or amplified peaking signal is conducted through a conductor (e.g., transmission line) having an electrical length of 180 degrees (e.g., half wavelength transmission line). The number of transistor fingers for each of the carrier and peaking amplifiers is proportional to the desired output power level. Thus, more transistor fingers are used for higher power amplifiers, which necessitates the use of relatively long output bond pads to interconnect the transistor finger outputs in such amplifiers. Unfortunately, at higher frequencies (e.g., in the gigahertz (GHz) range), the distributed nature of the output bond pads used to combine numerous transistor fingers can result in significant and undesirable signal power loss. More specifically, as the wavelength of the amplified RF signal approaches the physical size of the transistor block, a relatively large phase difference may occur between the signals at the edge fingers of each of the amplifiers. A large phase difference may result in significant signal power loss, which in turn may translate into relatively poor power added efficiency at the circuit stage. Thus, there is a need for a more energy efficient doherty amplifier design that can support amplification at high frequencies with relatively low loss. Disclosure of Invention According to one aspect of the present invention, there is provided a multi-path amplifier comprising: a semiconductor die; A first and a second amplifier input and an amplifier output, the first and second amplifier inputs and the amplifier output being integrally formed with the semiconductor die, and At least two amplifier units positioned between the amplifier input and the amplifier output, wherein the at least two amplifier units are positioned adjacent to each other, and each of the at least two amplifier units comprises: a first transistor integrally formed with the semiconductor die, wherein the first transistor has a first transistor input and a first transistor output, wherein the first transistor input is coupled to the first amplifier input; A second transistor integrally formed with the semiconductor die, wherein the second transistor has a second transistor input and a second transistor output, wherein the second transistor input is coupled to the second amplifier input; A combining node coupled to the second transistor out