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CN-112514048-B - Integrated circuit with thin film resistor having metal wall

CN112514048BCN 112514048 BCN112514048 BCN 112514048BCN-112514048-B

Abstract

An Integrated Circuit (IC) (100) includes a substrate having a semiconductor surface layer (102), the semiconductor surface layer (102) having functional circuitry for performing at least one circuit function, and having an inter-level dielectric (ILD) layer on a metal layer (118) above the semiconductor surface layer (102). A Thin Film Resistor (TFR) layer is on the ILD layer. At least one vertical metal wall (108) is on at least two sides of the TFR. The metal wall includes at least 2 metal levels coupled by a filled via (126). The functional circuitry is external to the metal wall.

Inventors

  • Q.Z.Hong
  • H.GUO
  • B. J. Timmer
  • SHEEHAN GREGORY BERNARD

Assignees

  • 德克萨斯仪器股份有限公司

Dates

Publication Date
20260505
Application Date
20190725
Priority Date
20180727

Claims (20)

  1. 1. A method of manufacturing an integrated circuit, IC, the method comprising: Providing a substrate having a semiconductor surface layer with functional circuitry for performing at least one circuit function and having an inter-level dielectric layer, ILD layer, on a metal layer above the semiconductor surface layer; forming a thin film resistor, TFR, on the ILD layer, the TFR comprising a TFR layer; Forming at least one vertical metal wall on at least two sides of the TFR to reduce or eliminate the effect of dielectric damage by suppressing the dielectric damage; wherein the metal wall comprises at least 2 metal levels coupled by filled vias, and Wherein the functional circuitry is external to the metal wall.
  2. 2. The method of claim 1, wherein the TFR layer comprises silicon chrome or nickel chrome or NiCr.
  3. 3. The method of claim 2, wherein the TFR layer comprises doped polysilicon.
  4. 4. The method of claim 1 wherein the TFR layer has a thickness of 1 nm to 100 nm.
  5. 5. The method of claim 1, further comprising laser trimming the TFR.
  6. 6. The method of claim 1, wherein the metal walls each comprise at least 2 of the metal walls.
  7. 7. The method of claim 1, wherein the at least 2 metal levels of the metal wall comprise a plurality of metal islands that are staggered.
  8. 8. The method of claim 1, wherein the at least 2 metal levels of the metal wall share a minimum width on the IC.
  9. 9. The method of claim 1, wherein the metal wall is electrically isolated from the semiconductor surface layer.
  10. 10. The method of claim 1, wherein the sheet resistance of said TFR is 100 to 1000 Ω/≡.
  11. 11. An integrated circuit, IC, the IC comprising: A substrate having a semiconductor surface layer with functional circuitry for performing at least one circuit function and having an inter-level dielectric layer, ILD layer, on a metal layer above the semiconductor surface layer; thin film resistors, i.e. TFRs, on the ILD layer, including a TFR layer, and At least one vertical metal wall on at least two sides of the TFR, Wherein the metal wall comprises at least 2 metal levels coupled by a filled via and is configured to reduce or eliminate the effect of dielectric damage by suppressing the dielectric damage, and Wherein the functional circuitry is external to the metal wall.
  12. 12. The IC of claim 11, wherein the TFR layer comprises silicon chrome or nickel chrome or NiCr.
  13. 13. The IC of claim 11, wherein the TFR layer comprises doped polysilicon.
  14. 14. The IC of claim 11, wherein the TFR layer has a thickness of 1 nm to 100 nm.
  15. 15. The IC of claim 11, wherein the metal walls each comprise at least 2 of the metal walls.
  16. 16. The IC of claim 11, wherein the at least 2 metal levels of the metal wall comprise a plurality of metal islands that are staggered.
  17. 17. The IC of claim 11, wherein the at least 2 metal levels of the metal wall share a minimum width across the IC.
  18. 18. The IC of claim 11, wherein the metal wall is electrically isolated from the semiconductor surface layer.
  19. 19. The IC of claim 11, wherein the sheet resistance of the TFR is 100 to 1000 Ω/≡.
  20. 20. The IC of claim 11, wherein the IC comprises an analog IC.

Description

Integrated circuit with thin film resistor having metal wall Technical Field The present invention relates to a semiconductor Integrated Circuit (IC) device having a Thin Film Resistor (TFR). Background Some IC devices include TFR. The thickness of TFR is typically on the order of 0.1 μm or less, while the thickness of thick film resistors is typically 1000 times thicker. Silicon chromium (SiCr) and nickel chromium (NiCr) have been used for many years as TFR due to their high electrical resistance in thin film form, relatively low Temperature Coefficient of Resistance (TCR), and the ability to reliably carry relatively high current densities. TFR may be laser trimmed, particularly for precision ICs, such as for setting the offset voltage of an operational amplifier or the output voltage of a voltage regulator. Laser trimming is accomplished by ablating a portion of the TFR structure using a laser beam. As the effective cross-sectional area of TFR decreases, its resistance increases. Laser trimming is typically performed in conjunction with wafer probing. Disclosure of Invention This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description including the drawings that are provided. This summary is not intended to limit the scope of the claimed subject matter. An IC includes a substrate having a semiconductor surface layer with functional circuitry for performing at least one circuit function and an inter-level dielectric (ILD) layer on a metal layer over the semiconductor surface layer. TFR including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal wall includes at least 2 metal layers coupled together by a filled via. The functional circuitry is external to the metal wall. Drawings Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein: FIG. 1A depicts a cross-sectional view of a portion of an example IC having a TFR that includes a disclosed metal wall at least partially surrounding the TFR. Fig. 1B is a top view of the disclosed TFR having a metal wall at least partially surrounding the TFR by enclosing 3 of the 4 sides of the TFR. Fig. 1C is a cross-sectional view of the IC shown with TFR at least partially surrounding the 3 metal walls shown in fig. 1B. Fig. 2A-2J are cross-sectional views illustrating process progression of an example method of forming an IC having metal walls at least partially surrounding TFR, according to an example aspect. Detailed Description Example aspects are described with reference to the drawings, wherein like reference numerals are used to refer to like or equivalent elements. The illustrated sequence of acts or events is not to be taken in a limiting sense, as some acts or events may occur in different orders and/or concurrently with other acts or events. Moreover, some illustrated acts or events may not be required to implement a methodology in accordance with the present disclosure. Furthermore, the term "coupled to" or "coupled with" as used herein (and the like), without further limitation, is intended to describe an indirect or direct electrical connection. Thus, if a first device "couples" to a second device, that connection may be through a direct electrical connection where only parasitics are present in the path, or through an indirect electrical connection via intermediaries including other devices and connections. For indirect coupling, the intermediate term typically does not modify the information of the signal, but may adjust its current level, voltage level, and/or power level. The present disclosure recognizes that possible dielectric damage generated during laser trimming of TFR can lead to quality and reliability risks of the IC, such as increased leakage current and reduced mechanical strength. The disclosed IC has a TFR with an at least partially surrounding metal wall that can reduce or eliminate the effects of laser trimming induced dielectric damage by suppressing the dielectric damage so that it does not extend beyond the metal wall. The disclosed metal walls include metal layers and filled vias (e.g., filled tungsten) coupling at least 2 different metal layers together. Fig. 1A depicts a cross-sectional view of a portion of an example IC 100 having a TFR 290, the TFR 290 including surrounding metal walls 108a and 108b at least partially surrounding the TFR 290. The IC 100 is formed on a substrate 102, such as a silicon wafer. The substrate 102 may comprise a bulk substrate material such as silicon or an epitaxial layer on a bulk substrate material. Alternatively, the substrate may comprise silicon germanium, other group 4 materials, or other semiconductor materials including III-V and II-VI compound semiconductor materials. The IC 100 includes at least one TFR, shown as TFR 290, each end of which is connected to a first node and a second node, respect