CN-112582005-B - Voltage multiplexing selection circuit for EEPROM port and EEPROM system comprising same

CN112582005BCN 112582005 BCN112582005 BCN 112582005BCN-112582005-B

Abstract

The invention provides a voltage multiplexing selection circuit for an EEPROM port and an EEPROM system comprising the same, wherein the voltage multiplexing selection circuit comprises a control line end and a bit line end voltage check module, the control line end voltage check module comprises a first latch, a first latch signal input unit, a first output switch tube and a second output switch tube, the grid electrodes of the first output switch tube and the second output switch tube are respectively connected with the output end of the first latch, the drain electrodes of the first output switch tube and the second output switch tube are respectively used for receiving first input voltage and second input voltage, the source electrodes of the first output switch tube and the second output switch tube are respectively connected with the control line ends of different storage units, the bit line end voltage check module comprises a second latch, a second latch signal input unit, a third output switch tube and a fourth output switch tube, the grid electrodes of the third output switch tube and the fourth output switch tube are respectively connected with the output end of the second latch, the drain electrodes of the third output switch tube and the fourth output switch tube are respectively used for receiving third input voltage and fourth input voltage, and the source electrodes of the second output switch tube are respectively connected with the bit line ends of different storage units. The invention can solve the problems of complex structure of EEPROM port voltage multiplexing selection circuit and more analog devices.

Inventors

ZHAO BEN

Assignees

上海贝岭股份有限公司

Dates

Publication Date: 20260508
Application Date: 20201224

Claims (7)

1. The voltage multiplexing selection circuit for the EEPROM port is characterized by comprising a control line end voltage check module and a bit line end voltage check module; The control line end voltage check module comprises a first latch, a first latch signal input unit, a first output switching tube and a second output switching tube, wherein the first latch signal input unit is connected with the input end of the first latch; the grid electrodes of the first output switch tube and the second output switch tube are respectively connected with the output end of the first latch, the drain electrodes are respectively used for receiving a first input voltage and a second input voltage, and the source electrodes are respectively connected with the control line ends of different storage units in the EEPROM; the bit line end voltage check module comprises a second latch, a second latch signal input unit, a third output switch tube and a fourth output switch tube, wherein the second latch signal input unit is connected with the input end of the second latch, grid electrodes of the third output switch tube and the fourth output switch tube are respectively connected with different output ends of the second latch, drain electrodes of the third output switch tube and the fourth output switch tube are respectively used for receiving third input voltage and fourth input voltage, and source electrodes of the third output switch tube and the fourth output switch tube are respectively connected with bit line ends of different storage units in the EEPROM.
2. The voltage multiplexing selection circuit of claim 1, wherein, The first latch comprises a first inverter and a second inverter which are connected end to end; the second latch includes a third inverter and a fourth inverter connected end to end.
3. The voltage multiplexing selection circuit of claim 2, wherein, The first inverter comprises a first PMOS tube and a first NMOS tube, wherein the drain electrode of the first PMOS tube is used for receiving programming voltage, the source electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube, and the source electrode of the first NMOS tube is grounded; The second inverter comprises a second PMOS tube and a second NMOS tube, wherein the drain electrode of the second PMOS tube is used for receiving programming voltage, the source electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube and the grid electrode of the first NMOS tube, the grid electrode of the second NMOS tube is connected with the grid electrode of the second NMOS tube and the drain electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded.
4. The voltage multiplexing selection circuit of claim 2, wherein, The third inverter comprises a third PMOS tube and a third NMOS tube, wherein the drain electrode of the third PMOS tube is used for receiving programming voltage, the source electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, the grid electrode of the third PMOS tube is connected with the grid electrode of the third NMOS tube, and the source electrode of the third NMOS tube is grounded; The fourth inverter comprises a fourth PMOS tube and a fourth NMOS tube, wherein the drain electrode of the fourth PMOS tube is used for receiving programming voltage, the source electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube and the grid electrode of the third NMOS tube, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the fourth NMOS tube and the drain electrode of the third NMOS tube, and the source electrode of the fourth NMOS tube is grounded.
5. The voltage multiplexing selection circuit of claim 1, wherein the first latch signal input unit comprises a first input switch tube and a second input switch tube, wherein the grid electrode of the first input switch tube is connected with the grid electrode of the second input switch tube and is used for receiving a switch signal, the drain electrode of the first input switch tube and the drain electrode of the second input switch tube are used for receiving signals with opposite levels, and the source electrode of the first input switch tube and the source electrode of the second input switch tube are respectively connected with different input ends of the first latch.
6. The voltage multiplexing selection circuit of claim 1, wherein the second latch signal input unit comprises a third input switch tube and a fourth input switch tube, the gates of the third input switch tube and the fourth input switch tube are connected and used for receiving switch signals, the drains of the third input switch tube and the fourth input switch tube are used for receiving signals with opposite levels, and the sources of the third input switch tube and the fourth input switch tube are respectively connected with different input ends of the second latch.
7. An EEPROM system, comprising a first memory cell and a second memory cell, the first memory cell and the second memory cell respectively comprise a memory tube, a drain select tube connected with a drain electrode of the memory tube, and a gate select tube connected with a gate electrode of the memory tube, wherein the drain electrode of the drain select tube is connected with a bit line terminal of a corresponding memory cell, the drain electrode of the gate select tube is connected with a control line terminal of the corresponding memory cell, and the gate electrode of the drain select tube and the gate electrode of the gate select tube are respectively connected with word line terminals, the EEPROM system is characterized in that: voltage multiplexing selection circuit according to any of the preceding claims 1-6.

Description

Voltage multiplexing selection circuit for EEPROM port and EEPROM system comprising same Technical Field The present invention relates to the field of electronic technology, and in particular, to a voltage multiplexing selection circuit for an EEPROM port and an EEPROM system including the same. Background With the development of integrated circuit technology, electrically erasable Programmable read-only memory (ELECTRICALLY ERASE Programmable ROM, EEPROM) has been widely used, and the center of gravity of design and production of various manufacturers is gradually moved toward the direction of cost reduction and efficiency improvement. The EEPROM generally has a structure as shown in FIG. 1, and comprises a first memory cell 1 and a second memory cell 2, wherein the first memory cell 1 comprises a memory tube M0, a selection tube M2 (denoted as drain selection tube M2) connected with the drain of the memory tube M0, a selection tube M4 (denoted as gate selection tube M4) connected with the gate of the memory tube M0, and the second memory cell 2 comprises a memory tube M1, a selection tube M3 (denoted as drain selection tube M3) connected with the drain of the memory tube M1, and a selection tube M5 (denoted as gate selection tube M5) connected with the gates of the memory tubes M0 and M1. The drains of the drain selection tubes M2 and M3 are respectively connected with bit line ends BL0 and BL1 of the corresponding memory cells, the drains of the gate selection tubes M4 and M5 are respectively connected with control line ends CL0 and CL1 of the corresponding memory cells, the gates of the drain selection tubes M2 and M3 and the gate selection tubes M4 and M5 are connected with the same word line end WL, and the sources of the memory tubes M0 and M1 are respectively connected with VGD ports. The data erasing, writing and reading operations for each memory cell in the EEPROM are realized by loading different voltages to three ports of each memory cell, as shown in the following table 1: TABLE 1 In table 1, FLOAT represents floating, HV represents high voltage, ROUT represents read, LV represents low voltage, and VB represents bias voltage. The prior art generally provides different voltages to different ports of each memory cell through a voltage multiplexing selection circuit. However, the existing voltage multiplexing selection circuit of the EEPROM port has complex structure, more analog devices and large occupied area. Disclosure of Invention In order to solve the problems of complex structure, more analog devices and large occupied area of the voltage multiplexing selection circuit of the EEPROM port in the prior art, the invention provides an improved voltage multiplexing selection circuit for the EEPROM port and an EEPROM system comprising the voltage multiplexing selection circuit. In order to achieve the above object, the present invention provides a voltage multiplexing selection circuit for an EEPROM port, including a control line terminal voltage check module and a bit line terminal voltage check module; The control line end voltage check module comprises a first latch, a first latch signal input unit, a first output switch tube and a second output switch tube, wherein the first latch signal input unit is connected with the input end of the first latch, grid electrodes of the first output switch tube and the second output switch tube are respectively connected with the output end of the first latch, drain electrodes are respectively used for receiving a first input voltage and a second input voltage, and source electrodes are respectively connected with control line ends of different storage units in the EEPROM; The bit line end voltage check module comprises a second latch, a second latch signal input unit, a third output switch tube and a fourth output switch tube, wherein the second latch signal input unit is connected with the input end of the second latch, grid electrodes of the third output switch tube and the fourth output switch tube are respectively connected with different output ends of the second latch, drain electrodes of the third output switch tube and the fourth output switch tube are respectively used for receiving third input voltage and fourth input voltage, and source electrodes of the third output switch tube and the fourth output switch tube are respectively connected with bit line ends of different storage units in the EEPROM. In a preferred embodiment of the invention, the first latch comprises a first inverter and a second inverter which are connected end to end, and the second latch comprises a third inverter and a fourth inverter which are connected end to end. In a preferred embodiment of the present invention, the first inverter includes a first PMOS transistor and a first NMOS transistor, where a drain of the first PMOS transistor is configured to receive a programming voltage, a source is connected to a drain of the first NMOS transistor, a gate is connected to a g