CN-112768455-B - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

CN112768455BCN 112768455 BCN112768455 BCN 112768455BCN-112768455-B

Abstract

A semiconductor device capable of being used as a memory device is disclosed. The memory device includes a plurality of memory cells, and each memory cell includes a first transistor and a second transistor. The first transistor is disposed on a substrate comprising a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source electrode and the drain electrode of the second transistor are electrically connected to each other. The extremely low off-current of the second transistor allows the data stored in the memory cell to remain for a considerable time even without power.

Inventors

YAMAZAKI SHUNPEI

Assignees

株式会社半导体能源研究所

Dates

Publication Date: 20260505
Application Date: 20101007
Priority Date: 20091029

Claims (10)

1. A semiconductor device having a semiconductor substrate and a semiconductor substrate, Comprising a first transistor and a second transistor, The first transistor has a first channel formation region, The second transistor has a second channel formation region, The first channel formation region has silicon, The second channel formation region has an oxide semiconductor, A first insulating layer is disposed over the first channel formation region, The second channel formation region is disposed above the first insulating layer, A second insulating layer is disposed over the second channel formation region, A first conductive layer, a second conductive layer, and a third conductive layer are disposed over the second insulating layer, One of a source and a drain of the second transistor is electrically connected to a gate of the first transistor via the first conductive layer, One of a source and a drain of the first transistor is electrically connected to the second conductive layer, The other of the source and the drain of the first transistor is electrically connected to the third conductive layer, The first channel formation region does not have a region overlapping with the second channel formation region in a plan view, The second conductive layer is disposed to extend in a first direction in a plan view, The third conductive layer is disposed so as to extend in the first direction in a plan view, The first conductive layer is disposed so as to extend in a second direction intersecting the first direction in a plan view.
2. The semiconductor device of claim 1, wherein The gate of the second transistor is arranged to extend in the first direction in a plan view.
3. A semiconductor device includes a plurality of circuits arranged in a matrix, Wherein the circuit comprises a first transistor, a second transistor and a capacitor, The first transistor has a first semiconductor layer including a first channel formation region, The second transistor has a second semiconductor layer including a second channel formation region, The first channel formation region has silicon, The second channel formation region has an oxide semiconductor, A first conductive layer functioning as a source electrode or a drain electrode of the second transistor is in contact with an upper surface of a second conductive layer functioning as a gate electrode of the first transistor, has a region functioning as an electrode of the capacitor, The capacitor has a region overlapping with the gate electrode of the first transistor in a plan view, The second semiconductor layer has a region overlapping the first conductive layer, and is electrically connected to the second conductive layer via the first conductive layer.
4. A semiconductor device includes a plurality of circuits arranged in a matrix, Wherein the circuit comprises a first transistor, a second transistor and a capacitor, The first transistor has a first semiconductor layer including a first channel formation region, The second transistor has a second semiconductor layer including a second channel formation region, The first channel formation region has silicon, The second channel formation region has an oxide semiconductor, A first conductive layer functioning as a source electrode or a drain electrode of the second transistor is in contact with an upper surface of a second conductive layer functioning as a gate electrode of the first transistor, has a region functioning as an electrode of the capacitor, The capacitor has a region overlapping with the gate electrode of the first transistor in a plan view, The gate electrode of the first transistor does not overlap with the gate electrode of the second transistor in a plan view, The second semiconductor layer has a region overlapping the first conductive layer, and is electrically connected to the second conductive layer via the first conductive layer.
5. A semiconductor device includes a plurality of circuits arranged in a matrix, Wherein the circuit comprises a first transistor, a second transistor and a capacitor, The first transistor has a first semiconductor layer including a first channel formation region, The second transistor has a second semiconductor layer including a second channel formation region, The first channel formation region has silicon, The second channel formation region has an oxide semiconductor, A first conductive layer functioning as a source electrode or a drain electrode of the second transistor is in contact with an upper surface of a second conductive layer functioning as a gate electrode of the first transistor, has a region functioning as an electrode of the capacitor, The capacitor has a region overlapping with the gate electrode of the first transistor in a plan view, The second semiconductor layer is arranged to overlap with the capacitor and the gate electrode of the first transistor in a plan view, The second semiconductor layer has a region overlapping the first conductive layer, and is electrically connected to the second conductive layer via the first conductive layer.
6. A semiconductor device includes a plurality of circuits arranged in a matrix, Wherein the circuit comprises a first transistor, a second transistor and a capacitor, The first transistor has a first semiconductor layer including a first channel formation region, The second transistor has a second semiconductor layer including a second channel formation region, The first channel formation region has silicon, The second channel formation region includes an oxide semiconductor, A first conductive layer functioning as a source electrode or a drain electrode of the second transistor is in contact with an upper surface of a second conductive layer functioning as a gate electrode of the first transistor, has a region functioning as an electrode of the capacitor, The capacitor has a region overlapping with the gate electrode of the first transistor in a plan view, The gate electrode of the first transistor does not overlap with the gate electrode of the second transistor in a plan view, The second semiconductor layer is arranged to overlap with the capacitor and the gate electrode of the first transistor in a plan view, The second semiconductor layer has a region overlapping the first conductive layer, and is electrically connected to the second conductive layer via the first conductive layer.
7. A semiconductor device includes a plurality of circuits arranged in a matrix, Wherein the circuit comprises a first transistor, a second transistor and a capacitor, The first transistor has a first channel formation region, The second transistor has a second channel formation region, The first channel formation region has silicon, The second channel formation region has an oxide semiconductor layer, The upper surfaces of the source electrode and the drain electrode of the second transistor are connected with the oxide semiconductor layer, A gate electrode of the second transistor is arranged above the oxide semiconductor layer with a gate insulating layer of the second transistor interposed therebetween.
8. A semiconductor device includes a plurality of circuits arranged in a matrix, Wherein the circuit comprises a first transistor, a second transistor and a capacitor, The first transistor has a first channel formation region, The second transistor has a second channel formation region, The first channel formation region has silicon, The second channel formation region has an oxide semiconductor layer, The upper surface and the side surface of each of the source electrode and the drain electrode of the second transistor are connected to the oxide semiconductor layer, The gate electrode of the second transistor is arranged to overlap with the oxide semiconductor layer through a gate insulating layer of the second transistor.
9. The semiconductor device according to claim 7 or 8, wherein The first channel formation region is formed in the semiconductor layer.
10. The semiconductor device according to claim 7 or 8, wherein The first channel formation region is formed on a monocrystalline silicon substrate.

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers The present application is a divisional application proposed again for divisional application 201610082458.5. The divisional application 201610082458.5 is a divisional application of PCT international application No. PCT/JP2010/068103, international application No. 10/7 of 2010, application No. 201080049673.6 of the application entering the national stage of china, entitled "semiconductor device". Technical Field The invention disclosed herein relates to a semiconductor device using a semiconductor element, and a method for manufacturing the semiconductor device. Background Memory devices using semiconductor elements are broadly divided into two types, volatile devices that lose stored data when power is stopped, and nonvolatile devices that retain stored data even when power is not supplied. A typical example of the volatile memory element is DRAM (dynamic random access memory). The DRAM stores data in such a manner that transistors included in the storage element are selected and charges are stored in the capacitor. When data is read from the DRAM, the charge in the capacitor is lost according to the principles described above, and thus, another write operation is necessary each time the data is read. Further, the transistor included in the memory element has a leakage current, and charges flow into or out of the capacitor even when the transistor is not selected, so that the data holding time is short. Thus, it is necessary that another write operation (refresh operation) is performed at predetermined intervals, and it is difficult to sufficiently reduce power consumption. Furthermore, since stored data is lost when power is stopped, an additional storage element using a magnetic material or an optical material is required to hold the data for a long time. Another example of a volatile storage element is SRAM (static random access memory). SRAM retains stored data by using circuits such as flip-flops, and thus does not require refresh operations. This means that SRAM has advantages over DRAM. However, the cost per storage capacity increases due to the use of circuits such as flip-flops. Furthermore, as in DRAM, stored data in SRAM is lost when power is stopped. A typical example of a nonvolatile memory element is a flash memory. Flash memory includes a floating gate between a gate electrode and a channel formation region in a transistor, and stores data by holding charges in the floating gate. Therefore, the flash memory has an advantage in that the data holding time is extremely long (almost permanent), and a refresh operation that is necessary in the volatile memory device is not required (for example, see patent document 1). However, the gate insulating layer included in the memory element is degraded by a tunneling current generated at the time of writing, so that the memory element stops its function after a plurality of writing operations. To avoid this problem, for example, a method of compensating the number of write operations to the memory element is adopted. However, complex ancillary circuitry is additionally required to implement this approach. Furthermore, the basic problem of lifetime is not solved with this approach. In other words, flash memory is not suitable for applications in which data is frequently rewritten. In addition, high voltages are necessary to inject charge into the floating gate or remove charge. Further, it takes a relatively long time to inject or remove the electric charges, and writing and erasing are not easily performed at a higher speed. [ Reference ] Patent document 1 Japanese laid-open patent application No. S57-105889 Disclosure of Invention In view of the above, it is an object of one embodiment of the invention disclosed herein to provide a semiconductor device having a novel structure in which stored data can be held even when power is not supplied, and in which there is no limitation on the number of times of writing. One embodiment of the present invention is a semiconductor device having a layered structure of a transistor formed using an oxide semiconductor and a transistor formed using a material other than the oxide semiconductor. For example, the following structure can be adopted. An embodiment of the present invention is a semiconductor device including a first line (source line), a second line (bit line), a third line (first signal line), a fourth line (second signal line), a first transistor having a first gate electrode, a first source electrode, and a first drain electrode, and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is disposed on a substrate comprising a semiconductor material. The second transistor includes an oxide semiconductor layer. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each o