CN-112787662-B - Clock data recovery system and device, storage medium and electronic device

CN112787662BCN 112787662 BCN112787662 BCN 112787662BCN-112787662-B

Abstract

The invention provides a clock data recovery system, a clock data recovery device, a storage medium and an electronic device, wherein the clock data recovery system comprises a sampling clock module, a first analog-to-digital conversion module, a second analog-to-digital conversion module and a sampling clock phase module, wherein the sampling clock module is configured to generate a first sampling clock signal and a second sampling clock signal, the first analog-to-digital conversion module is configured to acquire an analog input signal and the first sampling clock signal and acquire a first output signal, the second analog-to-digital conversion module is configured to acquire the analog input signal and the second sampling clock signal and acquire a second output signal, and the sampling clock module is further configured to acquire a sampling clock phase signal and generate the first sampling clock signal and the second sampling clock signal according to the sampling clock phase signal. The invention can solve the problem that the clock data recovery device in the related technology can not realize the clock data recovery efficiently, thereby achieving the effect of improving the clock data recovery efficiency.

Inventors

LU XIAOFAN
YI SHENGTAO
SHEN XIONGJIE

Assignees

深圳市中兴微电子技术有限公司

Dates

Publication Date: 20260512
Application Date: 20191108

Claims (15)

1. A clock data recovery system, comprising: a sampling clock module configured to generate a first sampling clock signal and a second sampling clock signal; the first analog-to-digital conversion module is configured to acquire an analog input signal and the first sampling clock signal, and sample the analog input signal according to the first sampling clock signal to acquire a first output signal; the second analog-to-digital conversion module is configured to acquire an analog input signal and the second sampling clock signal, and sample the analog input signal according to the second sampling clock signal to acquire a second output signal; the sampling clock module is further configured to obtain a sampling clock phase signal, and generate the first sampling clock signal and the second sampling clock signal according to the sampling clock phase signal, wherein the sampling clock phase signal is a phase signal obtained by performing phase discrimination processing and filtering processing according to the first output signal and the second output signal; The phase discrimination module is configured to acquire the first output signal and the second output signal, and perform phase discrimination processing and filtering processing on the first output signal and the second output signal to generate the sampling clock phase signal; The phase discrimination module comprises a splicing unit, an equalization unit, a phase discrimination unit, a filtering unit and a phase generation unit, wherein the splicing unit is configured to splice the first output signal and the second output signal in the time domain to obtain spliced signals, the equalization unit is configured to perform equalization processing on the spliced signals to obtain equalized spliced signals, the phase discrimination unit is configured to perform phase discrimination processing on the equalized spliced signals to obtain phase discrimination signals, the filtering unit is configured to perform loop filtering processing on the phase discrimination signals to obtain filtered phase discrimination signals, and the phase generation unit is configured to generate the sampling clock phase signals according to the filtered phase discrimination signals.
2. The system of claim 1, wherein the sampling rate of the first analog-to-digital conversion module is the same as the data symbol rate in the analog input signal.
3. The system of claim 2, wherein the sampling rate of the first analog-to-digital conversion module is the same as the sampling rate of the second analog-to-digital conversion module or the sampling rate of the first analog-to-digital conversion module is different from the sampling rate of the second analog-to-digital conversion module.
4. The system of claim 2, wherein the sampled signal accuracy of the first analog-to-digital conversion module is the same as the sampled signal accuracy of the second analog-to-digital conversion module or the sampled signal accuracy of the first analog-to-digital conversion module is different from the sampled signal accuracy of the second analog-to-digital conversion module.
5. The system of claim 2, wherein the sampling clock phase of the first analog-to-digital conversion module is different from the sampling clock phase of the second analog-to-digital conversion module.
6. The system of any one of claims 1 to 5, wherein the first analog-to-digital conversion module is comprised of a plurality of analog-to-digital converters in a time-interleaved configuration, and the second analog-to-digital conversion module is comprised of a plurality of analog-to-digital converters in a time-interleaved configuration.
7. A method for recovering clock data, comprising: Acquiring a first output signal output by a first analog-to-digital conversion module and a second output signal output by a second analog-to-digital conversion module, and recovering clock data according to the first output signal and/or the second output signal; The first output signal is obtained by sampling the analog input signal according to a first sampling clock signal by the first analog-to-digital conversion module, the second output signal is obtained by sampling the analog input signal according to a second sampling clock signal by the second analog-to-digital conversion module, the first sampling clock signal and the second sampling clock signal are both generated according to sampling clock phase signals, the sampling clock phase signals are phase signals obtained by phase discrimination processing and filtering processing according to the first output signal and the second output signal, the phase discrimination processing comprises the steps of splicing the first output signal and the second output signal in the time domain to obtain a spliced signal, equalizing the spliced signal to obtain the equalized spliced signal, performing phase discrimination processing on the equalized spliced signal to obtain a phase discrimination signal, performing loop filtering processing on the phase discrimination signal to obtain the phase discrimination signal, and generating the phase discrimination signal according to the filtered phase discrimination signal.
8. The method of claim 7, wherein prior to obtaining the first output signal output by the first analog-to-digital conversion module and the second output signal output by the second analog-to-digital conversion module, further comprising: And acquiring the first output signal and the second output signal, and carrying out phase discrimination processing on the first output signal and the second output signal to generate sampling clock phase signals.
9. The method according to any of claims 7 to 8, wherein the sampling rate of the first analog-to-digital conversion module is the same as the data symbol rate in the analog input signal.
10. The method of claim 9, wherein the sampling rate of the first analog-to-digital conversion module is the same as the sampling rate of the second analog-to-digital conversion module or the sampling rate of the first analog-to-digital conversion module is different from the sampling rate of the second analog-to-digital conversion module.
11. The method of claim 9, wherein the sampled signal accuracy of the first analog-to-digital conversion module is the same as the sampled signal accuracy of the second analog-to-digital conversion module or the sampled signal accuracy of the first analog-to-digital conversion module is different from the sampled signal accuracy of the second analog-to-digital conversion module.
12. The method of claim 9, wherein the sampling clock phase of the first analog-to-digital conversion module is different from the sampling clock phase of the second analog-to-digital conversion module.
13. A clock data recovery apparatus provided on a receiving side, the apparatus comprising: The acquisition module is used for acquiring a first output signal output by the first analog-to-digital conversion module and a second output signal output by the second analog-to-digital conversion module, and recovering clock data according to the first output signal and/or the second output signal; The first output signal is obtained by sampling the analog input signal according to a first sampling clock signal by the first analog-to-digital conversion module, the second output signal is obtained by sampling the analog input signal according to a second sampling clock signal by the second analog-to-digital conversion module, the first sampling clock signal and the second sampling clock signal are both generated according to sampling clock phase signals, the sampling clock phase signals are phase signals obtained by phase discrimination processing and filtering processing according to the first output signal and the second output signal, the phase discrimination processing comprises the steps of splicing the first output signal and the second output signal in the time domain to obtain a spliced signal, equalizing the spliced signal to obtain the equalized spliced signal, performing phase discrimination processing on the equalized spliced signal to obtain a phase discrimination signal, performing loop filtering processing on the phase discrimination signal to obtain the phase discrimination signal, and generating the phase discrimination signal according to the filtered phase discrimination signal.
14. A storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of claims 7 to 12 when run.
15. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of any of the claims 7 to 12.

Description

Clock data recovery system and device, storage medium and electronic device Technical Field The present invention relates to the field of communications, and in particular, to a clock data recovery system and apparatus, a storage medium, and an electronic apparatus. Background The clock data restorer is used for estimating correct sampling time and outputting sampling data for a receiver of a high-speed serial communication system (SERDES), and estimating intersymbol interference (Inter Symbol Interference, ISI) possibly caused by errors. Therefore, in the high-speed serial communication system, the clock data restorer is one of functional modules that directly affects the performance of the high-speed serial communication system. In the related art, in order to increase the data rate, the high-speed serial communication system currently has two evolution directions, namely, a faster symbol rate is adopted, i.e. the symbol period is shortened, and a higher order modulation is adopted for modulating more signal bits per transmission symbol. Aiming at the evolution requirement of the high-speed serial communication system, the performance requirement of the clock data restorer is also improved. At present, the clock data restorer in the related art still cannot meet the increasingly developed high-speed serial communication system in terms of performance, or cannot adapt to the scenes such as high-order modulation and the like although the clock data restorer is reliable in performance. In view of the above-mentioned problem that the clock data restorer cannot realize efficient clock data restoration in the related art, no effective solution has been proposed in the related art. Disclosure of Invention The embodiment of the invention provides a clock data recovery system and device, a storage medium and an electronic device, which at least solve the problem that a clock data recoverer in the related art cannot realize clock data recovery efficiently. According to an embodiment of the present invention, there is provided a clock data recovery system including: a sampling clock module configured to generate a first sampling clock signal and a second sampling clock signal; the first analog-to-digital conversion module is configured to acquire an analog input signal and the first sampling clock signal, and sample the analog input signal according to the first sampling clock signal to acquire a first output signal; the second analog-to-digital conversion module is configured to acquire an analog input signal and the second sampling clock signal, and sample the analog input signal according to the second sampling clock signal to acquire a second output signal; The sampling clock module is further configured to obtain a sampling clock phase signal, and generate the first sampling clock signal and the second sampling clock signal according to the sampling clock phase signal, wherein the sampling clock phase signal is a phase signal obtained by performing phase discrimination processing and filtering processing according to the first output signal and the second output signal. According to another embodiment of the present invention, there is also provided a clock data recovery method including: acquiring a first output signal output by a first analog-to-digital conversion module and a second output signal output by a second analog-to-digital conversion unit, and recovering clock data according to the first output signal and/or the second output signal; The first output signal is obtained by sampling the analog input signal by the first analog-to-digital conversion module according to a first sampling clock signal, the second output signal is obtained by sampling the analog input signal by the second analog-to-digital conversion module according to a second sampling clock signal, the first sampling clock signal and the second sampling clock signal are both generated according to sampling clock phase signals, and the sampling clock phase signals are phase signals obtained by phase discrimination processing and filtering processing according to the first output signal and the second output signal. According to another embodiment of the present invention, there is also provided a clock data recovery apparatus including: The acquisition module is used for acquiring a first output signal output by the first analog-to-digital conversion module and a second output signal output by the second analog-to-digital conversion unit, and recovering clock data according to the first output signal and/or the second output signal; The first output signal is obtained by sampling the analog input signal by the first analog-to-digital conversion module according to a first sampling clock signal, the second output signal is obtained by sampling the analog input signal by the second analog-to-digital conversion module according to a second sampling clock signal, the first sampling clock signal and the second sampling clock signal are both g