CN-112836455-B - SOC simulation method and system

CN112836455BCN 112836455 BCN112836455 BCN 112836455BCN-112836455-B

Abstract

The application belongs to the field of chips, and provides an SOC simulation method and system, wherein the system comprises the following steps: an FPGA system and a software model system; the FPGA system is connected with the software model system through a first connecting interface and a second connecting interface to form an SOC simulation system; the system for simulating the SOC carries out modeling, integration, joint debugging simulation and verification of a high-level language on an IP to be developed based on a first SOC architecture so as to generate a second SOC architecture; and carrying out RTL modeling, integration and joint debugging simulation on the IP to be developed based on the second SOC architecture to form a third SOC architecture. By combining the FPGA system and the software model system, system-level software and hardware verification based on new IP can be performed in early stage, the research and development efficiency is improved, and the research and development success rate is improved through architecture rolling verification in later stage.

Inventors

QU SHENZHENG
WANG XIN

Assignees

上海擎昆信息科技有限公司
上海擎昆信息科技有限公司

Dates

Publication Date: 20231110
Application Date: 20210120
Priority Date: 20210120

Claims (8)

1. An SOC simulation system, comprising: an FPGA system and a software model system; the FPGA system is connected with the software model system through a first connecting interface and a second connecting interface to form an SOC simulation system; the system for simulating the SOC carries out modeling, integration, joint debugging simulation and verification of a high-level language on an IP to be developed based on a first SOC architecture so as to generate a second SOC architecture; the method specifically comprises the following steps: connecting and integrating the FPGA system based on the first SOC architecture with the software model system through the first connecting interface and the second connecting interface to form an SOC simulation system based on the second SOC architecture; when the software model system is communicated with the FPGA system, the software model data of the IP to be developed is sent to the FPGA system through the software model system; performing joint debugging simulation and verification on the second SOC architecture through the SOC simulation system and software debugging based on the second SOC architecture; the first SOC architecture integrates the IP of the existing RTL code; the SOC simulation system further performs RTL modeling, integration, joint debugging simulation on the IP to be developed based on the second SOC architecture to form a third SOC architecture, and specifically includes: RTL modeling is carried out on the IP to be developed through the software model system so as to generate an RTL module of the IP to be developed; and integrating the FPGA system and the RTL module of the IP to be developed, and performing joint debugging simulation and verification on the third SOC architecture.
2. The SOC simulation system of claim 1, wherein the FPGA system comprises: the bus conversion interface is used for converting the bus access signal of the FPGA system to the IP to be developed into an ETH/USB/UART interface access signal and a data packet; an ETH/USB/UART interface for transmitting an interface access signal and a data packet of the ETH/USB/UART to the software model system; receiving data packets of the software model data or the status signals of the IP to be developed returned by the software model system; and the interface conversion bus is used for converting the data packet received by the ETH/USB/UART interface into bus data of the FPGA system so as to transmit the bus data to a processor of the FPGA system.
3. The SOC simulation system of claim 1, wherein the FPGA system further comprises: the processor is used for integrating the developed IP into the FPGA system, receiving the bin file of the first SOC architecture and the software model data of the IP to be developed, and performing joint debugging simulation on the first SOC architecture; and the processor is further used for performing joint debugging simulation on the second SOC architecture based on the software model data of the IP to be developed.
4. The SOC simulation system of claim 2, wherein the software model system comprises: the software model of the IP to be developed is used for realizing the algorithm calculation of the IP to be developed and returning data or a state signal according to the interface access signal; the software model conversion interface is used for converting the return data or the state signal of the IP to be developed into an ETH/USB/UART interface access signal and a data packet; the ETH/USB/UART interface is used for sending interface access signals and data packets of the ETH/USB/UART to the FPGA system; receiving a bus access data packet sent to the software model of the IP to be developed by the FPGA system; and the interface is converted into a software model, and the software model is used for converting the FPGA bus access data packet received by the ETH/USB/UART interface into access information received by the software model of the IP to be developed.
5. An SOC simulation method, comprising: according to the SOC design specification requirement, integrating and developing the IP of the existing RTL code into a first SOC architecture; through developing a new IP software model, the system is integrated and connected to a first SOC architecture, and joint debugging simulation and verification are carried out to generate a second SOC architecture, and the system specifically comprises the following steps: connecting and integrating the FPGA system based on the first SOC architecture with the software model system through the first connecting interface and the second connecting interface to form an SOC simulation system based on the second SOC architecture; when the software model system is communicated with the FPGA system, the software model data of the new IP is sent to the FPGA system through the software model system; performing joint debugging simulation and verification on the second SOC architecture through the SOC simulation system and software debugging based on the second SOC architecture; through developing the RTL model of new IP, connect to the second SOC framework integrally, to carry on joint debugging emulation, verify, in order to form the third SOC framework, include specifically: RTL modeling is carried out on the new IP through the software model system so as to generate an RTL module of the new IP; and integrating the FPGA system and the RTL module of the new IP, and performing joint debugging simulation and verification on the third SOC architecture.
6. The SOC simulation method of claim 5, further comprising, before the integrating the software model by developing the new IP to the first SOC architecture and performing joint debugging simulation and verification to generate the second SOC architecture: designing a first SOC architecture including developed IP; integrating the developed IP into an FPGA system based on the RTL module of the developed IP; performing software modeling on the new IP to generate a software model of the new IP in the software model system; and developing software of the first SOC architecture to obtain a bin file of the first SOC architecture.
7. The SOC simulation method of claim 6, wherein the sending, by the software model system, the software model data of the new IP to the FPGA system when the software model system is in communication with the FPGA system, comprises: converting a bus access signal of the FPGA system accessing the new IP through a bus into an access signal of a first connection interface through a bus conversion interface of the FPGA system; transmitting the interface access signal of the new IP to the software model system through a first connection interface of the FPGA system; transmitting the software model data of the new IP to a first connection interface of the FPGA system through a second connection interface of the software model system; receiving the data and the state signals of the new IP returned by the software model system through a first connection interface of the FPGA system, and transmitting the data and the state signals to an interface conversion bus of the FPGA system; and converting the data and state signals of the new IP software model into bus data and state signals received by a processor of the FPGA system through an interface conversion bus of the FPGA system.
8. The SOC simulation method of claim 7, wherein the RTL modeling of the new IP by the software model system to generate an RTL module of the new IP comprises: directly transplanting the software based on the second SOC architecture to an SOC simulation system based on a third SOC architecture; and comparing data of the software model based on the second SOC architecture, and verifying the RTL model based on the third SOC architecture.

Description

SOC simulation method and system Technical Field The application relates to the field of chips, in particular to an SOC simulation method and system. Background In developing and designing an SOC chip, early software and hardware system verification is usually required on an FPGA platform. For the newly designed IP module in the project, modeling simulation is often performed through a high-level simulation language, for example, matlab-based algorithm simulation, C-based algorithm simulation and SystemC-based TLM transaction-level simulation, and finally, RTL code implementation and simulation verification are performed. The method in the prior art can not integrate new IP to perform software and hardware verification in early stage on the FPGA platform, thereby increasing project research and development time. Disclosure of Invention The application provides an SOC simulation method and system, which solve the problems. The technical scheme provided by the application is as follows: an SOC simulation system, comprising: an FPGA system and a software model system; the FPGA system is connected with the software model system through a first connecting interface and a second connecting interface to integrate an SOC simulation system; the system for simulating the SOC carries out modeling, integration, joint debugging simulation and verification of a high-level language on an IP to be developed based on a first SOC architecture so as to generate a second SOC architecture; and carrying out RTL modeling, integration and joint debugging simulation on the IP to be developed based on the second SOC architecture to form a third SOC architecture. Further preferably, the FPGA system includes: the bus conversion interface is used for converting the bus access signal of the FPGA system to the IP to be developed into an ETH/USB/UART interface access signal and a data packet; an ETH/USB/UART interface for transmitting an interface access signal and a data packet of the ETH/USB/UART to the software model system; receiving data packets of the software model data or the status signals of the IP to be developed returned by the software model system; and the interface conversion bus is used for converting the data packet received by the ETH/USB/UART interface into bus data of the FPGA system so as to transmit the bus data to a processor of the FPGA system. Further preferably, the FPGA system further comprises: the processor is used for integrating the developed IP into the FPGA system, receiving a software debugging bin file and carrying out joint debugging simulation on the first SOC architecture; the processor is further configured to integrate the software model of the IP to be developed, receive a software debug bin file and software model data of the IP to be developed, and perform joint debugging simulation on the second SOC architecture. The processor is further configured to integrate the RTL model of the IP to be developed, receive a software debug bin file and RTL model data of the IP to be developed, and perform joint debugging simulation on the third SOC architecture. Further preferably, the software model system includes: the software model of the IP to be developed is used for realizing the function algorithm calculation of the IP to be developed and returning data or a state signal according to the interface access signal; the software model conversion interface is used for converting the return data or the state signal of the IP to be developed into an ETH/USB/UART interface access signal and a data packet; the ETH/USB/UART interface is used for sending interface access signals and data packets of the ETH/USB/UART to the FPGA system; receiving a bus access data packet sent to the software model of the IP to be developed by the FPGA system; and the interface is converted into a software model, and the software model is used for converting the FPGA bus access data packet received by the ETH/USB/UART interface into access information received by the software model of the IP to be developed. . An SOC simulation method, comprising: according to the SOC design specification requirement, integrating and developing the IP of the existing RTL code into a first SOC architecture; through developing a new IP software model, integrating and connecting to the first SOC architecture, and performing joint debugging simulation and verification to generate a second SOC architecture; and (3) integrating and connecting to the second SOC architecture by developing an RTL model of the new IP, and performing joint debugging simulation and verification to form a third SOC architecture. Further preferably, before the joint debugging simulation and verification are performed on the first SOC architecture by the SOC simulation system to generate the second SOC architecture, the method further includes: designing a first SOC architecture including developed IP; integrating the developed IP into an FPGA system based on the RTL module of th