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CN-112905406-B - Leadless pacemaker and method for storing event data in leadless pacemaker

CN112905406BCN 112905406 BCN112905406 BCN 112905406BCN-112905406-B

Abstract

The invention relates to a leadless pacemaker (1) comprising a central processing unit (2), a first logic circuit (11) configured to generate event data based on a first event (E1) occurring during operation of the leadless pacemaker (1), a first hardware event counter (21) configured to increment if the first logic circuit (11) generates specific event data, a first memory unit (30) comprising a first bit configured to be set if the first hardware event counter (21) is incremented to a first maximum count number, a second memory unit (40) in communication with the first memory unit (30), wherein the central processing unit (2) is configured to transfer the first bit to the second memory unit (40), a first RAM event counter (51) in a random access memory of the leadless pacemaker (1), wherein the central processing unit (2) is configured to increment the first RAM event counter (51) if the first bit is transferred to the second memory unit (40). The invention also relates to a method for storing event data in a leadless pacemaker (1).

Inventors

  • K. Swinson
  • TAFF BRIAN M.
  • BAWCUM BENJAMIN W.
  • K-h. Freiburg
  • D. MILLER

Assignees

  • 百多力两合公司

Dates

Publication Date
20260512
Application Date
20201027
Priority Date
20191204

Claims (15)

  1. 1. A leadless pacemaker (1) comprising: a central processing unit (2) configured to control the operation of the leadless pacemaker, A first logic circuit (11) configured to generate event data based on a first event (E1) occurring during operation of the leadless pacemaker (1), wherein the first event (E1) may be described by a binary variable, A first hardware event counter (21) configured to increment if the first logic circuit (11) generates specific event data, A first memory unit (30) comprising a first bit configured to be set if the first hardware event counter (21) is incremented to a first maximum count number, A second memory unit (40) in communication with the first memory unit (30), wherein the central processing unit (2) is configured to periodically transfer the first bit to the second memory unit (40), -A first RAM event counter (51) in a random access memory of the leadless pacemaker (1), wherein the central processing unit (2) is configured to increment the first RAM event counter (51) if the first bit is transferred to a second memory unit (40).
  2. 2. The leadless pacemaker (1) according to claim 1, wherein leadless pacemaker (1) further comprises a second logic circuit (12) and a second hardware event counter (22), the second logic circuit (12) being configured to generate event data based on a second event (E2) occurring during operation of leadless pacemaker (1), the second hardware event counter (22) being configured to increment if the second logic circuit (12) generates specific event data, wherein the first memory unit (30) comprises a second bit configured to be set if the second hardware event counter (22) is incremented to a second maximum count number, and wherein the central processing unit (2) is configured to transfer the second bit to the second memory unit (40), and wherein the leadless pacemaker (1) comprises a second RAM event counter (52) in the random access memory of the leadless pacemaker (1), wherein the central processing unit (2) is configured to increment if the second bit is transferred from the first memory unit (22) to the second memory unit (40).
  3. 3. Leadless pacemaker (1) according to claim 1, characterized in that the event data generated from the first event (E1) is the value of the binary variable.
  4. 4. Leadless pacemaker (1) according to claim 1, characterized in that the first event (E1) is describable by a first binary variable and a second binary variable, wherein the event data generated from the first event (E1) is a third binary variable representing a combination of values of the first and second binary variable.
  5. 5. The leadless pacemaker (1) of claim 1 wherein the first event (E1) is describable by a binary variable and a metric variable, wherein the event data generated from the first event (E1) represents a combination of a value of the binary variable and a range of the metric variable.
  6. 6. The leadless pacemaker (1) of claim 1 wherein the leadless pacemaker (1) comprises a clock (70) configured to generate clock data (C).
  7. 7. The leadless pacemaker (1) of claim 6 wherein the first memory unit (30) is double buffered such that its contents may be transferred to the second memory unit (40) while the first memory unit (30) is cleared in a single operation, wherein the operation is clocked based on the clock data (C).
  8. 8. Leadless pacemaker (1) according to claim 2, characterized in that the central processing unit (2) is configured to periodically transfer the second bit to the second memory unit (40).
  9. 9. Leadless pacemaker (1) according to claim 2, characterized in that the first hardware event counter (21) and/or the second hardware event counter (22) are memory mapped or I/O mapped.
  10. 10. Leadless pacemaker (1) according to claim 1, characterized in that the first memory cell (30) and/or the second memory cell (40) is a register or latch, wherein the second memory cell (40) is a tri-state latch.
  11. 11. A method for storing event data in a leadless pacemaker (1), the leadless pacemaker (1) being a leadless pacemaker (1) according to claim 1, wherein event data is generated based on a first event (E1) occurring during operation of the leadless pacemaker (1), and wherein a first hardware event counter (21) is incremented if specific event data is generated based on the first event (E1), and wherein a first bit in a first memory unit (30) is set if the first hardware event counter (21) is incremented to a first maximum count number, and wherein the first bit is periodically transferred from a first memory unit (30) to a second memory unit (40), and wherein a first RAM event counter (51) in a random access memory of the leadless pacemaker (1) is incremented if the first bit is periodically transferred to the second memory unit (40), wherein the first event (E1) is describable by a binary variable.
  12. 12. The method of claim 11, wherein further event data is generated based on a second event (E2) occurring during operation of the leadless pacemaker (1), and wherein a second hardware event counter (22) is incremented if specific event data is generated based on the second event (E2), and wherein a second bit in the first memory unit (30) is set if the second hardware event counter (22) is incremented to a second maximum count number, and wherein the second bit is transferred from the first memory unit (30) to a second memory unit (40), and wherein a second RAM event counter (52) in the random access memory of the leadless pacemaker (1) is incremented if the second bit is transferred to the second memory unit (40).
  13. 13. The method according to claim 11, wherein the event data generated from the first event (E1) is a value of the binary variable, the first event (E1) being either a pacing delivered by a leadless pacemaker (1) or a ventricular perception detected by a leadless pacemaker (1).
  14. 14. The method of claim 11, wherein the first event (E1) is describable by a first binary variable and a second binary variable, wherein the event data generated from the first event (E1) is a third binary variable representing a combination of values of the first and second binary variables, wherein the first event (E1) is a cardiac cycle with atrial sense and ventricular pacing.
  15. 15. The method of claim 11, wherein the first event (E1) is describable by a binary variable and a metric variable, wherein the event data generated from the first event (E1) represents a combination of a value of the binary variable and a range of the metric variable, wherein the first event (E1) is a cardiac cycle having an atrial sense and a time interval between atrial senses within a particular range.

Description

Leadless pacemaker and method for storing event data in leadless pacemaker Technical Field The present invention relates to leadless cardiac pacemakers and methods of storing event data in leadless cardiac pacemakers. Background A pacemaker is an implantable device that delivers electrical pulses to the heart to stimulate the heart and maintain the heart rhythm of a heart patient. The leadless pacemaker is small enough to be implanted directly into the heart, and therefore lacks electrical leads leading from the pacemaker to the heart, as compared to conventional pacemakers implanted in subcutaneous locations. To monitor and optimize performance and monitor patient health, some pacemakers are capable of detecting, counting and storing events that occur during operation of the pacemaker. From the stored event data, pacemaker statistics, such as event counters, histograms (including a series of classified counters), and trends may be derived. A typical way to collect and store data in pacemakers according to the prior art is to use an event driven central processing unit (central processing unit, CPU) to process the events and analyze and classify them into counts, trends and histograms (so-called CPU-centric approaches). Wherein the CPU typically stores the resulting data in random access memory (random access memory, RAM) that can be queried and processed by a clinical programmer (programmer) for display to the user. Pacemaker events occur at each cardiac cycle. Waking up the CPU to process each event requires significant overhead to manage the context switch. Making event-related timing measurements may require that the CPU's energy expenditure be made higher than the expected CPU performance level, such as the need to support higher clock rates, the need to include additional timing peripherals, and the need to process complex software algorithms that keep the CPU active for longer periods of time. The CPU-centric approach has a significant impact on the service time of the pacemaker. Furthermore, alternative methods of using dedicated logic to collect and store data can increase the size of the integrated circuit, potentially affecting the volume of the pacemaker. Disclosure of Invention It is therefore an object of the present invention to provide a leadless pacemaker and a method of storing event data in a leadless pacemaker that is improved over the described drawbacks of the prior art, in particular a pacemaker that is capable of storing short-term statistics without invoking CPU operations and without imposing tight tolerances on the timing capabilities of the CPU. This object is achieved by the subject matter of independent claims 1 (leadless pacemaker) and 11 (method). Advantageous embodiments of the invention are claimed as dependent claims 2 to 10 and dependent claims 12 to 15 and are described hereinafter. A first aspect of the invention relates to a leadless pacemaker comprising at least the following components: A central processing unit configured to control operation of the leadless pacemaker, A first logic circuit configured to generate event data based on a first event occurring during operation of the leadless pacemaker, A first hardware event counter configured to increment if the first logic circuit generates the specific event data, A first memory unit comprising a first bit (bit) configured to be set, in particular to be set from 0 to 1, A second memory unit in communication with the first memory unit, wherein the central processing unit is configured to transfer the first bit from the first memory unit to the second memory unit, A first RAM event counter in the random access memory of the leadless pacemaker, wherein the central processing unit is configured to increment the first RAM event counter if the first bit is transferred to the second memory unit. In the context of the present specification, the term "leadless pacemaker" refers to an artificial cardiac pacemaker that may be directly implanted in the heart. As used herein, a "CPU" or "central processing unit" is a microprocessor configured to control the operation of a leadless pacemaker, which may include controlling the generation of voltages at the pacing electrodes of the leadless pacemaker, and controlling the sensing of electrical signals of the heart, as well as general control and organization of data processing. In the context of the present specification, the term "logic circuitry" refers to hardware components that perform processing functions in an embedded system of a leadless pacemaker according to the present invention. In particular, the logic circuit may incorporate selector logic configured to process two binary inputs into one binary output. Because they are hardware components, the logic circuits described herein function independently of the CPU and do not trigger CPU tasks. The logic circuit may receive input data related to events occurring during operation of the leadless pacemaker, in particular input