CN-112951288-B - Compensation circuit for compensating clock signal and memory device including the same

Abstract

A memory device includes a Delay Locked Loop (DLL), a clock compensation circuit, and a data input/output (I/O) circuit. The DLL outputs a first clock signal and a second clock signal. The clock compensation circuit adjusts the voltage level of the output node and generates an internal clock signal based on the voltage level of the output node. The data I/O circuit outputs data to the outside based on an internal clock signal. The clock compensation circuit includes a first pulse adjusting circuit and a second pulse adjusting circuit. The first pulse adjusting circuit is connected to the first output node and outputs a first adjusting current based on the first clock signal and a voltage level of the first output node. The second pulse adjusting circuit is connected to the second output node and outputs a second adjusting current based on the second clock signal and a voltage level of the second output node.

Inventors

• LIU CHANGYOU
• Lu Shouzheng

Assignees

• 三星电子株式会社

Dates

Publication Date

20260505

Application Date

20201120

Priority Date

20191211

Claims (20)

1. 1. A clock compensation circuit, comprising: a first switching circuit configured to determine whether to electrically connect the first node to the second node based on the first clock signal; a first pulse conditioning circuit connected to the first output node and configured to: Outputting a first regulated current based on the voltage level of the first output node when the second node is electrically disconnected from the first node, an Blocking the first regulated current in response to the first clock signal; a second switching circuit configured to determine whether to electrically connect the third node to the fourth node based on a second clock signal different from the first clock signal, and A second pulse conditioning circuit connected to the second output node and configured to: Outputting a second regulated current based on the voltage level of the second output node when the fourth node is electrically disconnected from the third node, an In response to the second clock signal, blocking the second regulated current, Wherein the first and second pulse adjusting circuits are configured to feed back the voltage of the first output node and the voltage of the second output node, respectively, to adjust the voltage level of the second node and the voltage level of the fourth node.
2. 2. The clock compensation circuit of claim 1, further comprising: a latch circuit connected to the first output node and the second output node and configured to output an output signal based on a voltage level of the first output node and a voltage level of the second output node, Wherein the clock compensation circuit is configured to generate a compensated clock signal based on an output signal output from the latch circuit.
3. 3. The clock compensation circuit of claim 1, Wherein the first switching circuit includes a transmission gate disposed between the first node and the second node, and Wherein the second switching circuit includes a transmission gate disposed between the third node and the fourth node.
4. 4. The clock compensation circuit of claim 1, Wherein, the first switching circuit: electrically disconnecting the first node from the second node when the voltage level of the first clock signal is the first level, an When the voltage level of the first clock signal is the second level, electrically connecting the first node to the second node, and Wherein the first level is different from the second level.
5. 5. The clock compensation circuit of claim 1, Wherein the first pulse adjusting circuit comprises a first transistor and a second transistor, Wherein the first transistor and the second transistor: Outputting a third regulated current to the first output node when the second node is electrically disconnected from the first node and the voltage level of the second node is the first level, an Blocking the third regulating current when the voltage level of the second node is a second level lower than the first level, and When the voltage level of the first output node reaches a first level, the first pulse adjusting circuit adjusts the voltage level of the second node to a second level.
6. 6. The clock compensation circuit of claim 5, Wherein the first pulse adjusting circuit further comprises a latch circuit disposed between the second node and the fifth node, Wherein the first transistor is a PMOS transistor disposed between the power supply terminal and the second transistor and receiving the first clock signal, an Wherein the second transistor is a PMOS transistor disposed between the first transistor and the first output node and receiving a voltage signal from the fifth node.
7. 7. The clock compensation circuit of claim 5, Wherein the first pulse adjusting circuit further comprises a third transistor and a fourth transistor, and Wherein the third transistor and the fourth transistor: When the second node is electrically disconnected from the first node and the voltage level of the first output node is the first level, a first regulated current is output from the second node to the ground terminal, and When the voltage level of the first output node is the second level, the first regulating current is blocked.
8. 8. The clock compensation circuit of claim 7, Wherein the third transistor is an NMOS transistor interposed between the second node and the fourth transistor and receiving a voltage signal from the first output node, an Wherein the fourth transistor is an NMOS transistor that is disposed between the third transistor and the ground terminal and receives the inverted first clock signal.
9. 9. The clock compensation circuit of claim 1, Wherein the second pulse adjusting circuit comprises a first transistor and a second transistor, Wherein the first transistor and the second transistor: Outputting a third regulated current from the second output node to the ground terminal when the fourth node is electrically disconnected from the third node and the voltage level of the fourth node is the second level, an When the voltage level of the fourth node is the first level higher than the second level, the third regulating current is blocked, Wherein the second pulse adjusting circuit adjusts the voltage level of the fourth node to the first level when the voltage level of the second output node reaches the second level, an Wherein the first output node and the second output node are the same node.
10. 10. The clock compensation circuit of claim 9, Wherein the second pulse adjusting circuit further comprises a latch circuit disposed between the fourth node and the sixth node, Wherein the first transistor is an NMOS transistor interposed between the second output node and the second transistor and receiving a voltage signal from the sixth node, and The second transistor is an NMOS transistor disposed between the first transistor and the ground terminal and receiving a second clock signal.
11. 11. The clock compensation circuit of claim 10, Wherein the second pulse adjusting circuit further comprises a third transistor and a fourth transistor, and Wherein the third transistor and the fourth transistor: outputting a second regulated current to the fourth node when the fourth node is electrically disconnected from the third node and the voltage level of the second output node is a second level, an When the voltage level of the second output node is the first level, the second regulating current is blocked.
12. 12. The clock compensation circuit of claim 11, Wherein the third transistor is a PMOS transistor which is interposed between the power supply terminal and the fourth transistor and receives the inverted second clock signal, and Wherein the fourth transistor is a PMOS transistor that is disposed between the third transistor and the fourth node and that receives a voltage from the second output node.
13. 13. A memory device, comprising: A delay locked loop DLL configured to output a first clock signal and a second clock signal different from the first clock signal; A clock compensation circuit connected to the output node and configured to: the voltage level of the output node is adjusted based on the first clock signal and the second clock signal, Generating an internal clock signal based on the voltage level of the output node, and A data input/output I/O circuit configured to output data to the outside of the memory device based on an internal clock signal, Wherein the clock compensation circuit includes: a first pulse adjusting circuit connected to the first output node and configured to determine whether to output the first adjusting current based on the first clock signal and the voltage level of the first output node, and And a second pulse adjusting circuit connected to the second output node and configured to determine whether to output the second adjusting current based on the second clock signal and a voltage level of the second output node.
14. 14. The memory device of claim 13, Wherein the first pulse adjusting circuit outputs a first adjusting current from the first node to the ground terminal when the voltage level of the first output node is a first level based on the first clock signal, and blocks the first adjusting current in response to the first clock signal, Wherein the second pulse adjusting circuit outputs a second adjusting current from the power supply terminal to the second node when the voltage level of the second output node is a second level different from the first level based on the second clock signal, and blocks the second adjusting current in response to the second clock signal, an Wherein the first output node and the second output node are the same node.
15. 15. The memory device of claim 13, Wherein the first pulse adjusting circuit outputs a first adjusting current from the power supply terminal to the first node when the voltage level of the first output node is a second level based on the first clock signal, and blocks the first adjusting current in response to the first clock signal, Wherein the second pulse adjusting circuit outputs a second adjusting current when the voltage level of the second output node is a second level based on the second clock signal, and blocks the second adjusting current in response to the second clock signal, an Wherein the first output node is different from the second output node.
16. 16. A clock compensation circuit, comprising: a first switching circuit configured to determine whether to electrically connect the first node to the second node based on the first clock signal; a first pulse conditioning circuit configured to: Outputting a first regulating current based on the voltage level of the first clock signal and the voltage level of the second node to regulate the voltage level of the first output node, and When the first node is electrically disconnected from the second node, feeding back the voltage of the first output node to adjust the voltage level of the second node; a second switching circuit configured to determine whether to electrically connect the third node to the fourth node based on a second clock signal different from the first clock signal, and A second pulse conditioning circuit configured to: Outputting a second regulating current based on the voltage level of the second clock signal and the voltage level of the fourth node to regulate the voltage level of the second output node, and When the third node is electrically disconnected from the fourth node, the voltage of the second output node is fed back to adjust the voltage level of the fourth node.
17. 17. The clock compensation circuit of claim 16, further comprising: a latch circuit connected to the first output node and the second output node and configured to output an output signal based on a voltage level of the first output node and a voltage level of the second output node, Wherein the clock compensation circuit is configured to generate a compensated clock signal for transmitting data to an external device based on an output signal output from the latch circuit.
18. 18. The clock compensation circuit of claim 17, wherein the first pulse adjustment circuit comprises: A logic gate configured to perform a logic operation on the voltage level of the first clock signal and the voltage level of the second node, and And a transistor configured to output the first regulated current to the second node depending on a voltage level of the first output node.
19. 19. The clock compensation circuit of claim 18, wherein the logic gate is a NAND gate disposed between the second node and the first output node.
20. 20. The clock compensation circuit of claim 18, wherein the transistor is a PMOS transistor disposed between a power supply terminal and the second node and receiving the voltage signal from the first output node.

Description

Compensation circuit for compensating clock signal and memory device including the same Cross Reference to Related Applications The present application is based on the priority of korean patent application No. 10-2019-0164400 filed in the korean intellectual property office on the date of claim 2019, 12 and 11, the disclosure of which is incorporated herein by reference in its entirety. Technical Field Embodiments of the inventive concept described herein relate to a compensation circuit, and more particularly, to a compensation circuit for compensating a clock signal and a memory device including the same. Background Semiconductor memory devices may be classified as either volatile memory devices or nonvolatile memory devices. Volatile memory devices refer to memory devices that lose data stored therein when power is turned off. As volatile memory devices, dynamic Random Access Memory (DRAM) is being used in various devices such as mobile systems, servers, and graphics devices. The memory device may operate in synchronization with a clock applied from outside the memory device. The memory device may include a delay locked loop (delay locked loop, DLL). The DLL may delay a clock applied from the outside and may generate an internal clock used in the memory device. Based on the internal clock, the memory device may control components in the memory device or may send data to the memory controller. The clock generation circuit of the memory device may generate the clock pulse signal based on an internal clock having a period set by a user or a memory controller. However, in the case where the clock pulse signal is not output from the clock generation circuit due to process, voltage, and temperature (PVT) variations, the memory device may not transmit data to the memory controller, or data transmission may be delayed. Disclosure of Invention Embodiments of the inventive concept provide a compensation circuit for compensating an internal clock signal. According to an example embodiment, a clock compensation circuit may include a first switching circuit, a first pulse adjusting circuit, a second switching circuit, and a second pulse adjusting circuit. The first switching circuit may determine whether to electrically connect the first node to the second node based on the first clock signal, the first pulse adjusting circuit may be connected to the first output node, and when the second node is electrically disconnected from the first node, may output the first adjusting current based on a voltage level of the first output node, and may block the first adjusting current in response to the first clock signal. The second switching circuit may determine whether to electrically connect the third node to the fourth node based on a second clock signal different from the first clock signal. The second pulse adjusting circuit may output a second adjusting current based on a voltage level of the second output node when the fourth node is electrically disconnected from the third node, and may block the second adjusting current in response to the second clock signal. The first and second pulse adjusting circuits may feed back the voltage of the first output node and the voltage of the second output node and may adjust the voltage level of the second node and the voltage level of the fourth node. According to an example embodiment, a memory device may include a Delay Locked Loop (DLL), a clock compensation circuit, and a data input/output (I/O) circuit. The DLL may output a first clock signal and a second clock signal different from the first clock signal. The clock compensation circuit is connected to the output node and may adjust a voltage level of the output node based on the first clock signal and the second clock signal, and may generate an internal clock signal based on the voltage level of the output node. The data I/O circuit may output data to the outside of the memory device based on an internal clock signal. The clock compensation circuit may include a first pulse adjusting circuit and a second pulse adjusting circuit. The first pulse adjusting circuit is connected to the first output node and may determine whether to output the first adjusting current based on the first clock signal and a voltage level of the first output node. The second pulse adjusting circuit is connected to the second output node and may determine whether to output the second adjusting current based on the second clock signal and a voltage level of the second output node. According to an example embodiment, the clock compensation circuit may include a first switching circuit, a first pulse adjusting circuit, a second switching circuit, and a second pulse adjusting circuit. The first switching circuit may determine whether to electrically connect the first node to the second node based on the first clock signal. The first pulse adjusting circuit may output a first adjusting current based on a voltage level of the first clock signal and a voltag