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CN-113140236-B - Memory die, memory device, and electronic device

CN113140236BCN 113140236 BCN113140236 BCN 113140236BCN-113140236-B

Abstract

A memory die includes a first bank including a first memory cell, a second bank including a second memory cell, a first local processor connected to the first bank local input/output line, transmitting first local bank data of the first bank through the first bank local input/output line, and configured to perform a first local calculation on the first local bank data, a second local processor connected to the second bank local input/output line, transmitting second local bank data of the second bank through the second bank local input/output line, and configured to perform a second local calculation on the second local bank data, and a global processor configured to control the first bank, the second bank, the first local processor, and the second local processor, and to perform a global calculation on a first local calculation result of the first local calculation and a second local calculation result of the second local calculation.

Inventors

  • WU CHENGYI

Assignees

  • 三星电子株式会社

Dates

Publication Date
20260512
Application Date
20200925
Priority Date
20200116

Claims (19)

  1. 1. A memory die, comprising: a first memory bank including a first memory cell; a second memory bank including a second memory cell; A first local processor connected to a first bank local input/output line through which first local bank data of the first bank is transferred, the first local processor being configured to perform a first local calculation on the first local bank data; A second local processor connected to a second bank local input/output line through which second local bank data of the second bank is transferred, the second local processor being configured to perform a second local calculation on the second local bank data, and A global processor configured to: controlling the first memory bank, the second memory bank, the first local processor, and the second local processor, and Performing a global computation on a first local computation result of the first local computation and a second local computation result of the second local computation, Wherein the first memory unit, the second memory unit, the control registers of the global processor, and the program buffers of the programs of the storage hosts of the global processor are mapped to memory addresses associated with the memory die, respectively.
  2. 2. The memory die of claim 1, wherein the first local processor comprises: an input multiplexer configured to: receiving the first local bank data through the first bank local input/output line, Receiving broadcast data broadcast by the global processor through a bank global input/output line, and Receiving local register data; A local processing element, LPE, array configured to perform the first local computation on at least one of the first local bank data, the broadcast data, and the local register data; a local register configured to store a first local calculation result of the first local calculation and output the first local calculation result as the local register data, and An output multiplexer configured to output the local register data to at least one of the first bank local input/output line, the bank global input/output line, and the input multiplexer.
  3. 3. The memory die of claim 2, further comprising: A bank global input/output strobe circuit configured to electrically connect the first bank local input/output line to the bank global input/output line under control of the global processor.
  4. 4. The memory die of claim 3, further comprising: An input/output sense amplifier configured to receive first local bank data output from the first bank and output the first local bank data to the first bank local input/output line; a write driver configured to write the first local bank data into the first memory cell, and A bank local input/output strobe circuit configured to electrically connect the write driver to the first bank local input/output line.
  5. 5. The memory die of claim 1, wherein the global processor comprises: a program buffer configured to store a program of the host; An instruction queue configured to store instructions of the program; An instruction decoder configured to decode instructions stored in the instruction queue; a first controller configured to control the first and second banks and the first and second local processors based on a result of decoding the instruction at the instruction decoder; A global processing element, GPE, array configured to perform the global computation based on a result of decoding the instruction at the instruction decoder; a global register configured to store a global calculation result of the global calculation; A data buffer configured to receive the first and second local computation results via a data bus, provide the first and second local computation results to the GPE array, and output the global computation results to the data bus, and A second controller configured to control the program buffer, the instruction queue, the instruction decoder, the first controller, the GPE array, the global register, and the data buffer.
  6. 6. The memory die of claim 5, wherein the global processor is further configured to: performing on-die processing by requesting data input/output of the first and second memory banks or the first and second local computations or performing the global computation in response to a start interrupt signal sent from the host, and When the on-die processing is fully performed, an end interrupt signal is sent to the host.
  7. 7. The memory die of claim 5, wherein the first controller is configured to: Bits identifying bank addresses of the first and second banks are processed as irrelevant bits and the first and second banks are controlled simultaneously.
  8. 8. A memory device, comprising: A first memory die comprising a first bank accessible through a channel, wherein the first memory die is configured to: Receiving a command for the first memory bank from a host through the channel, and Data input/output with the host through the channel based on the command, and A second memory die, comprising: A second memory bank that is capable of being accessed through the channel, A local processor configured to perform local computation on the data of the second memory bank, respectively, and A global processor configured to: controlling the second memory bank and the local processor, and Performing a global calculation on a local calculation result of the local calculation, Wherein the first bank, the second bank, the control registers of the global processor, and the program buffers of the global processor storing programs of the host are mapped to memory addresses associated with the memory device, respectively.
  9. 9. The memory device of claim 8, wherein the global processor is further configured to: on-die processing is performed by: Requesting data input/output of the second memory bank, or the local computation, or Executing the global computation in response to a start interrupt signal sent from the host, and When the on-die processing is fully performed, an end interrupt signal is sent to the host.
  10. 10. The memory device of claim 9, further comprising: The buffer die is provided with a buffer, Wherein the first memory die and the second memory die are stacked on the buffer die, an Wherein the path of the channel includes a plurality of through silicon vias TSVs passing through the buffer die, the first memory die, and the second memory die, respectively.
  11. 11. The memory device of claim 10, wherein the path of the channel is to transmit commands for the first bank and for data input/output with the host when the first memory die receives the commands and performs the data input/output and the global processor of the second memory die performs the on-die processing.
  12. 12. The memory device of claim 8, wherein the first memory die is implemented the same as the second memory die, Wherein the first memory die further comprises: A first local processor configured to perform a first local calculation on the data of the first memory bank, respectively, and A first global processor configured to: controlling the first memory bank and the first local processor, and Performing a first global computation on a local computation result of the first local computation, and Wherein the local computation is a second local computation, the local processor is a second local processor, and the global computation is a second global computation.
  13. 13. The memory device of claim 12, wherein the first global processor is further configured to: on-die processing is performed by: Requesting data input/output of the first memory bank, or the local computation, or Performing the local computation in response to a start interrupt signal sent from the host, and When the on-die processing is fully performed, an end interrupt signal is sent to the host.
  14. 14. The memory device of claim 8, wherein the first memory die is implemented differently than the second memory die.
  15. 15. An electronic device, comprising: a memory device including a first memory die and a second memory die, Wherein the first memory die includes a first memory bank, an Wherein the second memory die comprises: a second memory bank; A local processor configured to perform local computation on the data of the second memory bank, respectively, and A global processor configured to: Controlling the second memory bank and the local processor, and Performing global computation on a local computation result of the local computation, and A system on a chip comprising a memory controller configured to access one of the first memory die and the second memory die through a channel, Wherein the first bank, the second bank, the control registers of the global processor, and the program buffers of the programs of the storage hosts of the global processor are mapped to memory addresses associated with the memory devices, respectively.
  16. 16. The electronic device of claim 15, wherein the system-on-chip further comprises: A system processor configured to perform system processing by using the memory controller to access a first bank of the first memory die through the channel, and Wherein the global processor of the second memory die is configured to perform on-die processing by: Requesting data input/output of the second memory bank, or the local computation, or The global computation is performed while the system processor performs the system processing.
  17. 17. The electronic device of claim 16, wherein the memory device comprises: a buffer die, wherein the first memory die and the second memory die are stacked on the buffer die, and A path of a first channel between the buffer die and the first and second memory dies, an Wherein the path of the first channel is configured for the system processing when the system processor performs the system processing and the global processor of the second memory die performs the on-die processing.
  18. 18. The electronic device of claim 16, wherein the system process is an image process and the on-die process is a speech recognition process.
  19. 19. A memory die, comprising: A multi-die data bus configured to provide communication with a host, wherein the host is external to the memory die; a global processor directly coupled to the multi-die data bus, the global processor configured to: Executing video processing tasks in accordance with commands of the host, and Delegating the computationally intensive portion of the video processing task to a local processor; A first local bus strobe circuit coupled to the multi-die data bus and the local bus; A second local bus strobe circuit coupled to the local bus and to a memory bank; the memory bank; the local processor is coupled by: coupled to the multi-die data bus via the first local bus strobe circuit, and Coupled to the memory bank via the second local bus strobe circuit, Wherein the multi-die data bus, the global processor, the local bus, the first local bus gating circuit, the second local bus gating circuit, and the local processor are configured to efficiently use a limited bus bandwidth for high-speed data processing, wherein the high-speed data processing includes the video processing tasks.

Description

Memory die, memory device, and electronic device Cross Reference to Related Applications The present application claims priority from korean patent application No.10-2020-0005896 filed on 16 months 1 in 2020, the entire disclosure of which is incorporated herein by reference. Technical Field The present inventive concept relates to a memory die, a memory device, and an electronic device including a local processor and a global processor. Background Multiple semiconductor die may be stacked. Memory devices of three-dimensional structure can process large amounts of data at high speeds. To achieve a three-dimensional structure, multiple semiconductor dies may be stacked using through silicon vias (TVS). Today, even though data processing speeds increase, the separation of the processor from the memory can result in delays in the data transferred between the processor and the memory. To address this issue, in-memory Processing (PIM) may be used that is integrated with a processor and memory. Disclosure of Invention Embodiments provide a memory die, a memory device, and an electronic device that include a local processor and a global processor. According to an exemplary embodiment, a memory die includes a first bank, a second bank, a first local processor connected to the first bank local input/output line, transmitting first local bank data of the first bank through the first bank local input/output line, and configured to perform a first local calculation on the first local bank data, a second local processor connected to the second bank local input/output line, transmitting second local bank data of the second bank through the second bank local input/output line, and configured to perform a second local calculation on the second local bank data, and a global processor configured to control the first bank, the second bank, the first local processor, and the second local processor, and to perform a global calculation on a first local calculation result of the first local calculation and a second local calculation result of the second local calculation. A memory die is provided that includes a first memory bank including a first memory cell, a second memory bank including a second memory cell, a first local processor connected to the first memory bank local input/output line through which first local bank data of the first memory bank is transferred, the first local processor configured to perform a first local calculation on the first local bank data, a second local processor connected to the second memory bank local input/output line through which second local bank data of the second memory bank is transferred, the second local processor configured to perform a second local calculation on the second local bank data, and a global processor configured to control the first memory bank, the second memory bank, the first local processor, and the second local processor and perform a global calculation on a first local calculation result of the first local calculation and a second local calculation result of the second local calculation. There is also provided a memory device including a first memory die including a first memory bank accessible through a channel, wherein the first memory die is configured to receive a command for the first memory bank from a host through the channel and to input/output data with the host through the channel based on the command, and a second memory die including a second memory bank accessible through the channel, a local processor configured to perform local calculations on data of the second memory bank, respectively, and a global processor configured to control the second memory bank and the local processor and to perform global calculations on a result of the local calculations. Also provided herein is an electronic device comprising a memory device comprising a first memory die and a second memory die, wherein the first memory die comprises a first memory bank, and wherein the second memory die comprises a second memory bank, a local processor configured to perform local computations on data of the second memory bank, respectively, and a global processor configured to control the second memory bank and the local processor and perform global computations on local computation results of the local computations, and a system on a chip comprising a memory controller configured to access one of the first memory die and the second memory die through a channel. Also provided herein is a memory die comprising a multi-die data bus configured to provide communication with a host, wherein the host is external to the memory die, a global processor directly coupled to the multi-die data bus, the global processor configured to perform video processing tasks upon command of the host and delegate computationally intensive portions of the video processing tasks to the local processor, a first local bus gating circuit coupled to the multi-die data bus and the local bus, a second local bus gating