CN-113204501-B - Cache memory device and method of operating the same, and system including the cache memory device

Abstract

A cache memory device is disclosed that includes a cache circuit and a way prediction circuit. The cache circuit generates a cache hit signal indicating whether target data corresponding to the access address is stored in the cache line, and performs a current cache access operation mainly for the candidate way based on the candidate way signal indicating the candidate way in the way prediction mode. The way prediction circuit stores the accumulated information by accumulating a cache hit result indicating whether the target data is stored in one way and a way prediction hit result indicating whether the target data is stored in one candidate way, based on a cache hit signal provided during a previous cache access operation. The way prediction circuit generates a candidate way signal by determining a candidate way of a current cache access operation based on the accumulated information in the way prediction mode.

Inventors

• ZHU XUANYU

Assignees

• 三星电子株式会社

Dates

Publication Date

20260505

Application Date

20201112

Priority Date

20200130

Claims (20)

1. 1. A cache storage device, comprising: A cache circuit comprising a plurality of ways, wherein each of the plurality of ways comprises a plurality of cache lines corresponding to a plurality of sets, and the cache circuit is configured to generate a cache hit signal indicating whether target data corresponding to an access address is stored in the plurality of cache lines, and to perform a current cache access operation for a candidate way of the plurality of ways based on the candidate way signal indicating the candidate way in a way prediction mode, and A way prediction circuit configured to store accumulated information by accumulating a cache hit result indicating whether the target data is stored in one of the plurality of ways and a way prediction hit result indicating whether the target data is stored in one of the candidate ways based on the cache hit signals provided during a plurality of previous cache access operations, and configured to generate the candidate way signals by determining candidate ways of the current cache access operation based on the accumulated information in the way prediction mode.
2. 2. The cache storage device of claim 1, wherein the way prediction circuit generates a prediction mode signal indicating enablement or disablement of the way prediction mode based on the accumulated information and provides the prediction mode signal to the cache circuit.
3. 3. The cache storage device of claim 2, wherein the cache circuitry is to perform a primary cache access operation for the candidate path when the prediction mode signal indicates enablement of the path prediction mode, and to perform a secondary cache access operation for other paths of the plurality of paths than the candidate path only when the target data is not stored in the candidate path.
4. 4. The cache storage device of claim 2, wherein the cache circuit performs normal cache access operations for all of the plurality of ways when the prediction mode signal indicates disabling of the way prediction mode.
5. 5. The cache storage device of claim 1, wherein the way prediction circuit comprises: A supplemental inference buffer configured to store eviction information regarding eviction data replaced by new data and deleted from the plurality of cache lines during a valid re-reference interval.
6. 6. The cache memory device of claim 5, wherein the way prediction circuit generates mask information related to protection data based on the eviction information and provides the mask information to the cache circuit, Wherein the protection data indicates the evicted data that was re-written to a cache line during the valid re-reference interval, an Wherein the cache circuit prevents the protection data from being deleted from the cache line at least once based on the masking information.
7. 7. The cache storage device of claim 5, wherein the eviction information comprises an address of the eviction data, a victim identifier indicating a processor that previously written the eviction data to a cache line, and an attacker identifier indicating a processor that deleted the eviction data from a cache line.
8. 8. The cache storage device of claim 7, wherein the way prediction circuit stores cache occupancy information indicating an identifier of a processor corresponding to data stored in the plurality of cache lines, and determines the victim identifier based on the cache occupancy information.
9. 9. The cache storage device of claim 5, wherein the effective re-reference interval is determined based on a product of a number of processors commonly accessing the cache circuit and a number of the plurality of ways.
10. 10. The cache memory device of claim 1, wherein the cache memory device is a shared cache memory device commonly accessed by a plurality of processors.
11. 11. The cache storage device of claim 10, wherein the way prediction circuit comprises: A differential diagnostic register configured to store the accumulated information by accumulating a plurality of diagnostic bit pairs during the plurality of previous cache access operations for each of the plurality of processors and each of the plurality of sets, wherein each diagnostic bit pair includes a cache hit bit indicating the cache hit result and a way prediction hit bit indicating the way prediction hit result, and Control logic configured to generate candidate way signals corresponding to a processor and set associated with the current cache access operation based on the plurality of diagnostic bit pairs stored in the differential diagnostic register.
12. 12. The cache storage device of claim 11, wherein the way prediction circuit further comprises: a path rank buffer configured to store, for each of the plurality of processors and each of the plurality of sets, priority information indicating an order in which the plurality of paths are included in the candidate path.
13. 13. The cache storage device of claim 12, wherein the control logic circuit dynamically updates the priority information per cache access operation based on the plurality of diagnostic bit pairs.
14. 14. The cache storage device of claim 12, wherein the control logic stores a plurality of way prediction windows corresponding to the plurality of processors and the plurality of sets, wherein each of the plurality of way prediction windows indicates a number of candidate ways corresponding to each processor and each set, and the control logic determines candidate ways corresponding to a processor and set associated with a current cache access operation based on the plurality of way prediction windows and the priority information.
15. 15. The cache storage device of claim 14, wherein the control logic circuit dynamically updates the plurality of way prediction windows per cache access operation based on the plurality of diagnostic bit pairs.
16. 16. The cache memory device of claim 1, wherein the cache memory device is a dedicated cache memory device that is accessed exclusively by a single processor.
17. 17. The cache storage device of claim 16, wherein the way prediction circuit comprises: A differential diagnostic register configured to store, for each of the single processor and the plurality of sets, the accumulated information by accumulating a plurality of diagnostic bit pairs during the plurality of previous cache access operations, wherein each diagnostic bit pair includes a cache hit bit indicating the cache hit result and a way prediction hit bit indicating the way prediction hit result, and Control logic configured to generate candidate way signals corresponding to the single processor and set associated with the current cache access operation based on the plurality of diagnostic bit pairs stored in the differential diagnostic register.
18. 18. The cache storage device of claim 17, wherein the way prediction circuit further comprises: a path rank buffer configured to store, for each of the single processor and the plurality of sets, priority information indicating an order in which the plurality of paths are included in the candidate path, and Wherein the control logic dynamically updates the priority information per cache access operation based on the plurality of diagnostic bit pairs.
19. 19. A system, comprising: One or more processors; A main storage device configured to store data for use by the one or more processors, and A cache storage device configured to store a portion of data stored in the primary storage device and configured to be accessed by the one or more processors prior to the one or more processors accessing the primary storage device, wherein the cache storage device comprises: A cache circuit comprising a plurality of ways, wherein each of the plurality of ways comprises a plurality of cache lines corresponding to a plurality of sets, and the cache circuit is configured to generate a cache hit signal indicating whether target data corresponding to an access address is stored in the plurality of cache lines, and to perform a current cache access operation for a candidate way of the plurality of ways based on the candidate way signal indicating the candidate way in a way prediction mode, and A way prediction circuit configured to store accumulated information by accumulating a cache hit result indicating whether the target data is stored in one of the plurality of ways and a way prediction hit result indicating whether the target data is stored in one of the candidate ways based on the cache hit signals provided during a plurality of previous cache access operations, and configured to generate the candidate way signal by determining a candidate way of the current cache access operation based on the accumulated information in the way prediction mode.
20. 20. A method of operating a cache storage device comprising a plurality of ways, each of the plurality of ways comprising a plurality of cache lines corresponding to a plurality of sets, the method comprising: Generating a cache hit signal indicating whether target data corresponding to the access address is stored in the plurality of cache lines; Storing accumulated information by accumulating a cache hit result indicating whether the target data is stored in one of the plurality of ways and a way prediction hit result indicating whether the target data is stored in one of the candidate ways, based on the cache hit signals provided during a plurality of previous cache access operations; generating a candidate path signal by determining a candidate path for a current cache access operation of the plurality of paths based on the accumulated information in a path prediction mode, and The current cache access operation is performed for the candidate way based on the candidate way signal in the way prediction mode.

Description

Cache memory device and method of operating the same, and system including the cache memory device Cross Reference to Related Applications The present application claims priority from korean patent application No.10-2020-0010921, filed by the Korean Intellectual Property Office (KIPO) on month 1 and 30 in 2020, the entire contents of which are incorporated herein by reference. Technical Field Exemplary embodiments of the inventive concept relate generally to semiconductor integrated circuits and, more particularly, to a cache memory device, a system including the cache memory device, and a method of operating the cache memory device. Background Accessing the cache memory device of the processor consumes a significant amount of power. The cache storage device includes a data array having a plurality of sets such that each set includes a plurality of cache lines (e.g., storage locations). The cache storage device also includes a plurality of ways such that each way includes a driver corresponding to a plurality of cache lines. In response to an instruction to access data stored in the cache storage device, all drivers corresponding to the multiple paths are enabled (e.g., activated) to drive a particular set of data arrays to the multiplexer. In parallel with enabling all drivers (e.g., concurrently), a tag lookup operation is performed to identify a particular cache line within the data array. Based on the result of the tag lookup operation, data provided via a single driver (corresponding to a single cache line) is selected as the output of the multiplexer. Assuming that only data from a single cache line is output based on the instruction, driving all paths for the set and performing tag lookup operations may result in power consumption inefficiency. Disclosure of Invention According to an exemplary embodiment of the inventive concept, a cache storage device includes a cache circuit and a way prediction circuit. The cache circuit includes a plurality of ways, and each of the plurality of ways includes a plurality of cache lines corresponding to a plurality of sets. The cache circuit generates a cache hit signal indicating whether target data corresponding to an access address is stored in a plurality of cache lines, and performs a current cache access operation for a candidate way of the plurality of ways based on a candidate way signal indicating the candidate way in a way prediction mode. The way prediction circuit stores accumulated information by accumulating a cache hit result indicating whether target data is stored in one of the plurality of ways and a way prediction hit result indicating whether target data is stored in one of the candidate ways, based on cache hit signals provided during a plurality of previous cache access operations. The way prediction circuit generates a candidate way signal by determining a candidate way of a current cache access operation based on the accumulated information in the way prediction mode. According to an exemplary embodiment of the inventive concept, a system includes one or more processors, a main storage device configured to store data used by the one or more processors, and a cache storage device configured to store a portion of the data stored in the main memory and configured to be accessed by the one or more processors before the one or more processors access the main storage device. The cache storage device includes a cache circuit and a path prediction circuit. The cache circuit includes a plurality of ways, and each of the plurality of ways includes a plurality of cache lines corresponding to a plurality of sets. The cache circuit generates a cache hit signal indicating whether target data corresponding to an access address is stored in a plurality of cache lines, and performs a current cache access operation for a candidate way of the plurality of ways based on a candidate way signal indicating the candidate way in a way prediction mode. The way prediction circuit stores accumulated information by accumulating a cache hit result indicating whether target data is stored in one of the plurality of ways and a way prediction hit result indicating whether target data is stored in one of the candidate ways, based on cache hit signals provided during a plurality of previous cache access operations. The way prediction circuit generates a candidate way signal by determining a candidate way of a current cache access operation based on the accumulated information in the way prediction mode. According to an exemplary embodiment of the inventive concept, a method for operating a cache storage device including a plurality of ways, each of the plurality of ways including a plurality of cache lines corresponding to a plurality of sets, includes generating a hit signal indicating whether target data corresponding to an access address is stored in the plurality of cache lines, storing accumulation information by accumulating a cache hit result indicating whether the tar