CN-113224132-B - Manufacturing method of SiC semiconductor component

CN113224132BCN 113224132 BCN113224132 BCN 113224132BCN-113224132-B

Abstract

The invention relates to the technical field of semiconductor components, in particular to a manufacturing method of a SiC semiconductor component, which mainly comprises the steps of taking a SiC substrate with a SiC epitaxial layer grown on the surface, growing a first mask layer on the SiC epitaxial layer, etching a definition area on the upper end face of the first mask layer, implanting a deep P well into the SiC epitaxial layer in the definition area, depositing a layer of oxide and polysilicon in the definition area after implanting the deep P well, forming a first side wall through etching, implanting an interlayer P well into the SiC epitaxial layer through the first side wall, etching a second side wall after depositing a layer of polysilicon in the interlayer P well with the first side wall, implanting a shallow P well into the SiC epitaxial layer through the second side wall, depositing a layer of polysilicon in the definition area with the first side wall and the second side wall, forming a photoresist on the surface of the polysilicon, and forming a shielding film for subsequent P+ ion implantation in the definition area. The invention effectively improves the voltage resistance of the SiCNMOSFET, and the MOSFET can be smaller.

Inventors

LI LONGSHENG
HONG JIANZHONG
LI CHUANYING

Assignees

上海瀚薪科技有限公司

Dates

Publication Date: 20260512
Application Date: 20210430

Claims (9)

1. A manufacturing method of a SiC semiconductor component is characterized by comprising the following steps: Firstly, taking a SiC substrate (11) with a SiC epitaxial layer (12) grown on the surface, growing a first mask layer (13) on the SiC epitaxial layer (12), and etching a definition area on the upper end surface of the first mask layer (13); Step two, implanting a deep P well (9) into the SiC epitaxial layer (12) in the defined area; step three, after the deep P well (9) is implanted, depositing a layer of oxide and polysilicon in the defined area, and forming a first side wall (14) by etching; step four, implanting an interlayer P well (10) into the SiC epitaxial layer (12) through the first side wall (14); step five, etching a second side wall (15) after depositing a layer of polysilicon in the interlayer P well (10) with the first side wall (14), and implanting a shallow P well (8) into the SiC epitaxial layer (12) through the second side wall (15); Step six, a layer of polysilicon is deposited in the defining area with the first side wall (14) and the second side wall (15), a layer of photoresistance is arranged on the surface of the polysilicon, then a shielding film for subsequent P+ ion implantation is formed in the defining area, a third side wall (16) is etched at the edge of the second side wall (15), and N+ ions (2) are implanted in the SiC epitaxial layer (12) through the third side wall (16); Removing the first mask layer (13), the first side wall (14), the second side wall (15) and the third side wall (16) on the upper end face of the SiC epitaxial layer (12), regrowing a second mask layer (17), removing the photoresist after exposing and etching to define a P+ region, exposing the SiC epitaxial layer (12) through etching, implanting P+ ions (4) on the upper end face of the SiC epitaxial layer (12), removing the second mask layer (17) after implanting the P+ ions (4), covering a carbon film on the upper part of the semiconductor for protection, and tempering the whole semiconductor to activate the implanted ion layer into a conductor; Removing a carbon protection layer on the upper end face of the tempered and activated SiC epitaxial layer (12), sequentially growing a gate oxide (5) and polysilicon (7), etching the polysilicon (7) to form a first window, growing a layer of dielectric layer (6) on the upper end face of the polysilicon (7), and etching the upper end face of the interlayer dielectric layer (6) to form a second window; Step nine, removing oxide in the second window area to expose the SiC epitaxial layer, and forming a Ni silicon compound (3) after deposited Ni metal tempering; and step ten, depositing a metal electrode conducting layer (1) above the semiconductor to finish the final assembly of the semiconductor.
2. The method of manufacturing a SiC semiconductor device according to claim 1, wherein the first mask layer (13) is etched by performing photoresist, exposure and development on an upper end surface of the first mask layer (13) to define a defined region, and the etching is performed by reactive ion etching of the first mask layer (13) by plasma generated by glow discharge of a fluoride gas.
3. A method of fabricating a SiC semiconductor device as defined in claim 1, wherein the deep P-well (9) implant in step two is at an angle of 4 DEG or 0 DEG to the SiC epitaxial layer (12).
4. The method of manufacturing a SiC semiconductor device according to claim 1, wherein the depths of the deep P-well (9), the interlayer P-well (10) and the shallow P-well (8) in the second, fourth and fifth steps are varied, and the deep P-well (9) is deepest, the interlayer P-well (10) is shallower, and the shallow P-well (8) is shallowest.
5. The method of manufacturing a SiC semiconductor device according to claim 1, wherein the etching in the third, fifth and sixth steps is reactive ion etching, and etching is performed until the surface of the SiC epitaxial layer (12) is exposed.
6. The method of manufacturing a SiC semiconductor device as claimed in claim 1, wherein the masking region of the photoresist in the sixth step is a central region of the well-defining region, and the region in which the N+ ions (2) are implanted is between the third sidewall (16) and the masking film left after the photoresist is etched, the implantation of the N+ ions (2) is self-aligned through the shallow P-well (8), and the N+ ions (2) are aligned with an upper end surface of the shallow P-well (8).
7. The method of manufacturing a SiC semiconductor device according to claim 1, wherein the second mask layer (17) grown in the seventh step has the same thickness as the first mask layer (13), and the P+ ions (4) extend into the shallow P-well (8) and the interlayer P-well (10).
8. The method of manufacturing a SiC semiconductor device according to claim 1, wherein the tempering activation temperature in the seventh step is 1500-2000 ℃.
9. The method of manufacturing a SiC semiconductor device according to claim 1, wherein the step eight is characterized in that the semiconductor is subjected to sacrificial oxidation as a whole after the carbon protective layer is removed, the first window area is larger than the second window area, and the edge of the first window is above the N+ ions (2), and the second window area is larger than the area of the P+ ions (4).

Description

Manufacturing method of SiC semiconductor component Technical Field The invention relates to the technical field of semiconductor components, in particular to a manufacturing method of a SiC semiconductor component. Background Silicon carbide (SiC) belongs to a third generation semiconductor material, has a wide forbidden band, has a breakdown electric field 10 times higher and a thermal conductivity three times higher than that of a conventional silicon device, can obtain the same withstand voltage with a withstand voltage layer of 1/10 thickness, and realizes low on-resistance, high-speed switching and high-temperature and high-pressure resistant operation, so that it is popular in power supplies, automobiles, railways, industrial equipment and household consumer electronic equipment. As third generation power semiconductor devices, siC power devices will become the dominant devices for future power converters. SiC MOSFETs are considered to be the most likely replacement of Si IGBTs currently in wide use because of their low on-resistance, high switching rate, and other performance advantages. In the conventional SiC MOSFET structure, the channel length, i.e., the distance between the P-well and the n+ conductor, is self-aligned using the marker point, and due to the short channel effect caused by the alignment error, the threshold voltage is reduced, the leakage is increased, and the VBD is reduced. Disclosure of Invention The present invention is directed to a method for fabricating a SiC semiconductor device, which solves the problems set forth in the background art. The manufacturing method of the SiC semiconductor component comprises the following steps: Firstly, taking a SiC substrate with a SiC epitaxial layer grown on the surface, growing a first mask layer on the SiC epitaxial layer, and etching a definition area on the upper end surface of the first mask layer; step two, implanting a deep P well into the SiC epitaxial layer in the defined area; Step three, depositing a layer of oxide and polysilicon in the defined area after implanting the deep P well, and forming a first side wall by etching; step four, implanting an interlayer P well into the SiC epitaxial layer through the first side wall; step five, etching a second side wall after depositing a layer of polysilicon in the interlayer P well with the first side wall, and implanting a shallow P well into the SiC epitaxial layer through the second side wall; Step six, a layer of polysilicon is deposited in the defining area with the first side wall and the second side wall, a layer of photoresistance is arranged on the surface of the polysilicon, then a shielding film for subsequent P+ ion implantation is formed in the defining area, a third side wall is etched at the edge of the second side wall, and N+ ions are implanted into the SiC epitaxial layer through the third side wall; Removing the first mask layer, the first side wall, the second side wall and the third side wall on the upper end face of the SiC epitaxial layer, growing a second mask layer again, removing the photoresist after exposing and etching to define a P+ region, exposing the SiC epitaxial layer by etching, implanting P+ ions into the upper end face of the SiC epitaxial layer, removing the second mask layer after implanting the P+ ions, covering a carbon film on the upper part of the semiconductor for protection, and tempering the whole semiconductor to activate the implanted ion layer into the semiconductor; Removing the carbon protective layer on the upper end surface of the tempered and activated SiC epitaxial layer, then growing gate oxide and polysilicon in sequence, etching the polysilicon to form a first window, growing a layer of interlayer dielectric layer on the upper end surface of the polysilicon, and finally etching the upper end surface of the interlayer dielectric layer to form a second window; step nine, removing the oxide in the second window area to expose the SiC epitaxial layer, and forming a Ni silicon compound after tempering deposited Ni metal; and step ten, depositing a metal electrode conducting layer above the semiconductor to finish the final assembly of the semiconductor. Preferably, before etching the first mask layer in the first step, a defined area is determined by photoresist application, exposure and development on the upper end surface of the first mask layer, and the etching mode is that plasma generated by fluoride gas glow discharge performs reactive ion etching on the first mask layer. Preferably, the deep P-well implant in the second step will have an angle of 4 ° or 0 ° with the SiC epitaxial layer. Preferably, the depths of the deep P-well, the interlayer P-well and the shallow P-well in the second, fourth and fifth steps are changed, and the deep P-well is deepest, the interlayer P-well is shallower, and the shallow P-well is shallowest. Preferably, the etching manner in the third, fifth and sixth steps is reactive ion etching, and et