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CN-113314567-B - Method for manufacturing display device

CN113314567BCN 113314567 BCN113314567 BCN 113314567BCN-113314567-B

Abstract

A method of manufacturing a display device includes forming a thin film transistor on a substrate and forming a planarization layer to cover the thin film transistor, forming a pixel defining layer on the planarization layer, which is electrically connected to a pixel electrode of the thin film transistor and exposes at least a central portion of the pixel electrode, and defining at least one groove having a closed curve shape at a position corresponding to a second non-display region. When the thin film transistor is formed, a voltage line is also formed at a position corresponding to the first non-display region. When at least one groove is formed, a portion of the planarization layer disposed between the pad region and the display region is simultaneously removed such that a portion of the voltage line between the pad region and the display region is exposed.

Inventors

  • Fang Qihao
  • Cui Yuanshuo

Assignees

  • 三星显示有限公司

Dates

Publication Date
20260505
Application Date
20210112
Priority Date
20200227

Claims (14)

  1. 1. A method of manufacturing a display device including a display region, a first non-display region located around the display region and including a pad region on one side of the first non-display region, and a second non-display region at least partially surrounded by the display region, the method comprising: forming a thin film transistor on a substrate at a position corresponding to the display region, and forming a planarization layer covering the thin film transistor; forming a pixel electrode electrically connected to the thin film transistor and a pixel defining layer exposing at least a central portion of the pixel electrode on the planarization layer, and Defining at least one groove extending from a surface of the substrate in a thickness direction of the substrate at a position corresponding to the second non-display area, the at least one groove having a closed curve shape, Wherein, when the thin film transistor is formed, a voltage line for applying a voltage to the display device is formed together with the thin film transistor at a position corresponding to the first non-display region, and When the at least one groove is formed, a portion of the planarization layer disposed between the pad region and the display region is simultaneously removed such that a portion of the voltage line between the pad region and the display region is exposed.
  2. 2. The method of claim 1, wherein the substrate has a multi-layer structure in which a first base layer, a first barrier layer, a second base layer, and a second barrier layer are sequentially stacked, and The at least one groove is defined to extend from the second barrier layer to at least a portion of the second base layer in the thickness direction of the substrate.
  3. 3. The method of claim 1, wherein a cap layer is formed over the entire substrate prior to the forming of the at least one trench, The cover layer is patterned to define openings in the cover layer at locations where the at least one groove is to be defined and between the pad region and the display region, and Forming the at least one groove and removing a portion of the planarization layer disposed between the pad region and the display region are performed via the opening.
  4. 4. A method according to claim 3, wherein the at least one trench is formed and the portion of the planarization layer disposed between the pad region and the display region is removed by performing dry etching using the cover layer as a mask.
  5. 5. The method of claim 3, wherein the capping layer comprises at least one of indium tin oxide, indium zinc oxide, tin zinc indium oxide, gallium zinc oxide, and gallium zinc indium oxide.
  6. 6. The method of claim 1, wherein when the portion of the planarization layer disposed between the pad region and the display region is removed, a first dam and a bank surrounding the display region are formed, and the voltage line is exposed in an adhesion region between the first dam and the bank.
  7. 7. The method of claim 6, further comprising: Forming an intermediate layer including an emission layer on the pixel electrode, and forming a counter electrode on the intermediate layer; Sequentially forming a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer on the counter electrode, and A through-hole is defined within the region defined by the at least one slot.
  8. 8. The method of claim 7, wherein the first inorganic encapsulation layer directly contacts the voltage line and the second inorganic encapsulation layer in the adhesion zone.
  9. 9. The method of claim 7, wherein the at least one groove comprises a first groove surrounding the through hole and a second groove between the first groove and the through hole and surrounding the through hole, The organic encapsulation layer fills the first trench, and The first inorganic encapsulation layer and the second inorganic encapsulation layer are in direct contact with each other within the second trench.
  10. 10. The method of claim 7, wherein the intermediate layer is broken and discontinuously formed by the at least one groove.
  11. 11. The method of claim 7, wherein the thin film transistor comprises a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, A first inorganic insulating layer is formed between the semiconductor layer and the gate electrode to correspond to the entire substrate, and a second inorganic insulating layer is formed between the gate electrode and the source and drain electrodes to correspond to the entire substrate, and The first inorganic encapsulation layer directly contacts the second inorganic insulation layer in the adhesion zone.
  12. 12. The method of claim 6, wherein the pixel defining layer is formed on the planarization layer and disposed between the pad region and the display region, and The pixel defining layer and the planarization layer are removed from the adhesion region when the at least one groove is formed.
  13. 13. The method of claim 1, wherein the voltage lines include a first voltage line and a second voltage line to which voltages different from each other are applied, The first voltage line includes a first main voltage line formed between the display region and the pad region to correspond to a first edge of the display region and a first connection unit extending from the first main voltage line to the pad region, The second voltage line includes a second main voltage line surrounding the rest of the display area except the first edge and a second connection unit extending from the second main voltage line to the pad area, and Respective portions of the first and second connection units between the pad region and the display region are exposed.
  14. 14. The method of claim 1, wherein the voltage line is a three-layer comprising a first metal layer, a second metal layer, and a third metal layer, and an etch rate of the second metal layer is greater than an etch rate of each of the first metal layer and the third metal layer.

Description

Method for manufacturing display device The present application claims priority from korean patent application No. 10-2020-0024472, filed on even 27 in year 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field One or more embodiments relate to a method of manufacturing a display device. Background With the rapid development of display technologies for visually representing electrical signal information, various display devices having excellent characteristics such as thin profile, light weight, and low power consumption have been developed. Recently, in order to enlarge a display area on which an image is displayed, a display device has been introduced in which physical buttons or the like are removed from the front face of the display device, and electronic components such as a camera and a sensor are disposed within the display area. Since the organic light emitting display device as the self-emission display device does not require an additional light source, the organic light emitting display device can be driven at a low voltage and can be manufactured to be light-weight and thin. In addition, the organic light emitting display device has good characteristics such as a wide viewing angle, high contrast, and fast response speed. However, the organic light emitting diode may be deteriorated due to moisture, oxygen, or the like, and thus it is necessary to prevent external moisture, oxygen, or the like from penetrating into the organic light emitting diode. Disclosure of Invention One or more embodiments include a method of manufacturing a display device, by which external moisture, oxygen, or the like can be effectively prevented from penetrating into the display device. Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the embodiments of the disclosure presented. According to one or more embodiments, a method of manufacturing a display device including a display region, a first non-display region and a second non-display region, the first non-display region being located around the display region and including a pad region on one side of the first non-display region, the second non-display region being at least partially surrounded by the display region, includes forming a thin film transistor on a substrate at a position corresponding to the display region and forming a planarization layer to cover the thin film transistor, forming a pixel defining layer on the planarization layer electrically connected to a pixel electrode of the thin film transistor and exposing at least a central portion of the pixel electrode, and defining at least one groove extending from a surface of the substrate in a thickness direction of the substrate at a position corresponding to the second non-display region, the at least one groove having a closed curve shape. When the thin film transistor is formed, a voltage line for applying a voltage to the display device is formed together with the thin film transistor at a position corresponding to the first non-display region. When at least one groove is formed, a portion of the planarization layer disposed between the pad region and the display region is simultaneously removed such that a portion of the voltage line between the pad region and the display region is exposed. The substrate may have a multi-layered structure in which a first base layer, a first barrier layer, a second base layer, and a second barrier layer are sequentially stacked, and at least one groove may be defined to extend from the second barrier layer to at least a portion of the second base layer in a thickness direction of the substrate. The cover layer may be formed on the entire substrate before the formation of the at least one groove, the cover layer may be patterned to define an opening in the cover layer at a position where the at least one groove is to be defined and at a position between the pad region and the display region, and forming the at least one groove and removing a portion of the planarization layer disposed between the pad region and the display region are performed via the opening. By performing dry etching using the capping layer as a mask, at least one trench may be formed, and a portion of the planarization layer disposed between the pad region and the display region may be removed. The capping layer may include at least one of indium tin oxide, indium zinc oxide, tin zinc indium oxide, gallium zinc oxide, and gallium zinc indium oxide. When a portion of the planarization layer disposed between the pad region and the display region is removed, a first dam and a bank surrounding the display region may be formed, and a voltage line may be exposed in an adhesion region between the first dam and the bank. The method may further include forming an intermediate layer including an emission layer on the pixel electrode and forming a c