CN-113380694-B - Interconnect structure, semiconductor structure and forming method thereof

Abstract

The present application provides structures and methods for reducing electromigration. An interconnect structure according to the present application includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesive layer sandwiched between the capping barrier layer and the dielectric layer. The adhesive layer has a crystallinity of between about 40% and about 70%. Embodiments of the application also relate to interconnect structures, semiconductor structures, and methods of forming the same.

Inventors

• HE YIZHEN
• LIN QIAN
• YU CHENGYE
• CHEN XINXING
• Xie Zhongru

Assignees

• 台湾积体电路制造股份有限公司

Dates

Publication Date

20260512

Application Date

20210226

Priority Date

20200910

Claims (20)

1. 1. An interconnect structure, comprising: a conductive member embedded in the dielectric layer; a covering barrier layer disposed over the conductive member and the dielectric layer and covering the conductive member, and An adhesive layer sandwiched between the capping barrier layer and the dielectric layer, Wherein the dielectric layer is an amorphous dielectric layer, the capping barrier layer is a crystalline capping barrier layer, the adhesion layer is partially crystalline and comprises a crystallinity between 40% and 70%, and a lattice mismatch between the capping barrier layer and the adhesion layer is lower than a lattice mismatch between the capping barrier layer and the dielectric layer.
2. 2. The interconnect structure of claim 1, wherein the dielectric layer comprises amorphous silicon oxide.
3. 3. The interconnect structure of claim 1, wherein the capping barrier layer comprises aluminum nitride.
4. 4. The interconnect structure of claim 1, wherein the adhesive layer is disposed over the conductive feature.
5. 5. The interconnect structure of claim 1, wherein the adhesion layer comprises beta silicon nitride.
6. 6. The interconnect structure of claim 1, wherein the adhesion layer comprises hexagonal silicon oxide, hexagonal silicon carbide, diamond cubic silicon, tetragonal titanium oxide, hexagonal chromium oxide, or hexagonal aluminum oxide.
7. 7. The interconnect structure of claim 1, further comprising: and a conductive cover layer disposed between the conductive member and the cover barrier layer.
8. 8. A semiconductor structure, comprising: A contact member located in the dielectric layer, the contact member comprising: A metal filling layer is arranged on the surface of the metal filling layer, A barrier layer disposed between the metal filling layer and the dielectric layer, and A conductive capping layer over the metal fill layer and the barrier layer; a cover barrier layer disposed over the conductive cover layer and the dielectric layer and covering the conductive cover layer, and An adhesive layer sandwiched between the capping barrier layer and the dielectric layer, The dielectric layer is an amorphous dielectric layer, the covering barrier layer is a crystalline covering barrier layer and comprises crystalline aluminum nitride or crystalline boron nitride, the bonding layer is partially crystalline, and the lattice mismatch between the covering barrier layer and the bonding layer is lower than the lattice mismatch between the covering barrier layer and the dielectric layer.
9. 9. The semiconductor structure of claim 8, wherein the dielectric layer comprises amorphous silicon oxide.
10. 10. The semiconductor structure of claim 8, wherein the conductive capping layer comprises cobalt.
11. 11. The semiconductor structure of claim 8, wherein the capping barrier layer comprises crystalline aluminum nitride.
12. 12. The semiconductor structure of claim 11, wherein the adhesion layer comprises a crystallinity of between 40% and 70%.
13. 13. The semiconductor structure of claim 8, wherein the barrier layer comprises titanium, titanium nitride, tantalum nitride, molybdenum, ruthenium, nickel nitride, tungsten nitride, copper nitride, manganese nitride, or cobalt nitride.
14. 14. A method of forming a semiconductor structure, comprising: receiving a workpiece, wherein the workpiece comprises a dielectric layer and a conductive component embedded in the dielectric layer, and the dielectric layer is an amorphous dielectric layer; Forming an adhesive layer on a top surface of the dielectric layer; annealing the work piece after forming the adhesive layer to partially crystallize the adhesive layer and increase the crystallinity of the adhesive layer, and A capping barrier layer is deposited over the adhesion layer and the conductive feature, wherein the capping barrier layer overlies the conductive feature, wherein the capping barrier layer is a crystalline capping barrier layer and comprises crystalline aluminum nitride or crystalline boron nitride, and a lattice mismatch between the capping barrier layer and the adhesion layer is lower than a lattice mismatch between the capping barrier layer and the dielectric layer.
15. 15. The method of claim 14, wherein the dielectric layer comprises amorphous silicon oxide and the conductive feature comprises copper and manganese.
16. 16. The method of claim 14, wherein, The partially crystallized adhesive layer has a crystallinity of between 40% and 70%.
17. 17. The method of claim 14, wherein depositing the capping barrier layer comprises using Atomic Layer Deposition (ALD).
18. 18. The method of claim 14, wherein the adhesion layer comprises silicon nitride, silicon oxide, silicon carbide, silicon, titanium oxide, chromium oxide, or aluminum oxide.
19. 19. The method of claim 14, further comprising: a cobalt layer is selectively deposited over the conductive features prior to forming the adhesion layer.
20. 20. The method according to claim 19, Wherein the adhesion layer is not present on the top surface of the cobalt layer after the adhesion layer is formed.

Description

Interconnect structure, semiconductor structure and forming method thereof Technical Field Embodiments of the present application relate to interconnect structures, semiconductor structures, and methods of forming the same. Background The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the development of ICs, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while its geometry (i.e., the smallest component or line that can be manufactured in a manufacturing process) has decreased. Such a downscaling process generally provides benefits by increasing production efficiency and reducing associated costs. But scaling down also increases the complexity of processing and manufacturing ICs. For example, to prevent degradation of the conductive member due to contact with an adjacent dielectric layer, the conductive member may be lined with a barrier layer and covered with a cover barrier layer. While existing interconnect structures are generally adequate for their intended purpose, they are not satisfactory in all respects. Disclosure of Invention Some embodiments of the present application provide an interconnect structure comprising a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer, wherein the adhesion layer comprises a crystallinity of between about 40% and about 70%. Further embodiments of the present application provide a semiconductor structure comprising a contact member in a dielectric layer, the contact member comprising a metal fill layer, a barrier layer disposed between the metal fill layer and the dielectric layer, and a conductive capping layer disposed over the metal fill layer and the barrier layer, a capping barrier layer disposed over the conductive capping layer and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer, wherein the capping barrier layer comprises aluminum nitride or boron nitride. Still further embodiments of the present application provide a method of forming a semiconductor structure comprising receiving a workpiece comprising a dielectric layer and a conductive feature embedded in the dielectric layer, forming an adhesion layer on a top surface of the dielectric layer, and depositing a capping barrier layer over the adhesion layer, wherein the capping barrier layer comprises aluminum nitride or boron nitride. Drawings Aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawing figures. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Fig. 1 illustrates a flow diagram of a method for forming an interconnect structure or portion of an interconnect structure in accordance with one or more aspects of the present invention. Fig. 2A, 2B, 3, 4A-7A and 4B-7B illustrate partial cross-sectional views of a workpiece undergoing various stages of operation in the method of fig. 1 in accordance with one or more aspects of the present invention. Detailed Description The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Spatially relative terms, such as "under", "below", "lower", "above", "upper", and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or op