CN-113497035-B - Semiconductor device including gate spacer

Abstract

A semiconductor device includes a first active region defined on a substrate, a first gate electrode crossing the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.

Inventors

• XU FENGXI
• JIN DAYUAN
• Pu Fanjin
• Pu Shuojiong
• Pu Xingyi
• SHEN ZAIXUN
• Yang Fengxie
• LIU TINGJUN
• LI ZAIRUN

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20201125

Priority Date

20200407

Claims (20)

1. 1. A semiconductor device, comprising: A first active region defined on the substrate; A first gate electrode crossing the first active region; A first drain region in the first active region at a position adjacent to the first gate electrode; an undercut region between the first active region and the first gate electrode, and A first gate spacer on a side surface of the first gate electrode and extending into the undercut region, Wherein the first gate spacer comprises: An upper portion on a side surface of the first gate electrode, and A lower portion extending from the upper portion into the undercut region, and Wherein the upper portion and the lower portion are integrally formed.
2. 2. The semiconductor device of claim 1, wherein the first gate spacer has an L-shape or an inverted T-shape.
3. 3. The semiconductor device of claim 1, wherein the lower portion extends between the first active region and the first gate electrode.
4. 4. The semiconductor device according to claim 1, wherein an imaginary straight line extending along a side surface of the first gate electrode and perpendicular to a surface of the substrate intersects the lower portion.
5. 5. The semiconductor device of claim 1, wherein, The first active region includes a plurality of channel regions, each of the plurality of channel regions being in contact with the first drain region, and The first gate electrode surrounds a top surface, side surfaces, and a bottom surface of at least one of the plurality of channel regions.
6. 6. The semiconductor device of claim 5, further comprising a first gate dielectric layer extending between the first gate electrode and the plurality of channel regions and between the first gate electrode and the first gate spacer, the first gate dielectric layer contacting side and top surfaces of the lower portion.
7. 7. The semiconductor device of claim 1, further comprising: a second active region defined on the substrate; a second gate electrode crossing the second active region; a second drain region in the second active region at a position adjacent to the second gate electrode; a lower gate dielectric layer between the second active region and the second gate electrode, and And a second gate spacer on a side surface of the second gate electrode.
8. 8. The semiconductor device of claim 7, wherein the second gate electrode is on a top surface and a side surface of the second active region, a lower end of the second gate electrode being at a lower level than an upper end of the second active region.
9. 9. The semiconductor device of claim 7, further comprising a second gate dielectric layer between the lower gate dielectric layer and the second gate electrode and extending between the second gate spacer and the second gate electrode.
10. 10. The semiconductor device of claim 7, wherein a horizontal width of the second gate electrode is greater than a horizontal width of the first gate electrode, and a horizontal width of the lower gate dielectric layer is greater than a horizontal width of the second gate electrode.
11. 11. The semiconductor device of claim 7, wherein the lower gate dielectric layer protrudes beyond the second gate electrode.
12. 12. The semiconductor device of claim 7, wherein the second gate spacer is in contact with a top surface and side surfaces of the lower gate dielectric layer.
13. 13. The semiconductor device of claim 7, wherein a horizontal width of the lower gate dielectric layer is less than a horizontal width of the second gate electrode, and the second gate spacer extends between the second active region and the second gate electrode.
14. 14. The semiconductor device of claim 13, wherein the second gate spacer has an L-shape or an inverted T-shape.
15. 15. A semiconductor device, comprising: a first active region defined in a first region on the substrate; A first gate electrode crossing the first active region; A first drain region in the first active region at a position adjacent to the first gate electrode; A first gate spacer on a side surface of the first gate electrode; a second active region defined in a second region on the substrate; a second gate electrode crossing the second active region and having a horizontal width different from that of the first gate electrode; a second drain region in the second active region at a position adjacent to the second gate electrode; A lower gate dielectric layer between the second active region and the second gate electrode and having a smaller width than that of the second gate electrode, and A second gate spacer on a side surface of the second gate electrode and extending into an undercut region between the second active region and the second gate electrode, the second gate spacer being in contact with a side surface of the lower gate dielectric layer, Wherein the second gate spacer comprises: an upper portion on a side surface of the second gate electrode, and A lower portion extending from the upper portion into the undercut region, and Wherein the upper portion and the lower portion are integrally formed.
16. 16. The semiconductor device of claim 15, wherein, The first active region includes a plurality of channel regions, each of the plurality of channel regions being in contact with the first drain region, The first gate electrode surrounds the top, side and bottom surfaces of at least one of the plurality of channel regions, and The second gate electrode is on a top surface and a side surface of the second active region, and a lower end of the second gate electrode is at a lower level than an upper end of the second active region.
17. 17. A semiconductor device, comprising: a first active region defined in a first region on the substrate; A first gate electrode crossing the first active region; A first gate dielectric layer between the first active region and the first gate electrode; a pair of first drain regions in the first active region at positions adjacent to opposite sides of the first gate electrode and spaced apart from each other; an undercut region between the first active region and the first gate electrode; a first gate spacer on a side surface of the first gate electrode and extending into the undercut region; a second active region defined in a second region on the substrate; a second gate electrode crossing the second active region and having a horizontal width greater than that of the first gate electrode; a second gate dielectric layer between the second active region and the second gate electrode; a pair of second drain regions in the second active region at positions adjacent to opposite sides of the second gate electrode and spaced apart from each other; A lower gate dielectric layer between the second active region and the second gate dielectric layer and having a horizontal width greater than that of the second gate electrode, and A second gate spacer on a side surface of the second gate electrode, Wherein the first active region includes a plurality of channel regions, each of the plurality of channel regions being in contact with the pair of first drain regions, Wherein the first gate electrode surrounds a top surface, a side surface, and a bottom surface of at least one of the plurality of channel regions, Wherein the second gate electrode is on a top surface and a side surface of the second active region, a lower end of the second gate electrode is at a lower level than an upper end of the second active region, Wherein the first gate spacer comprises: An upper portion on a side surface of the first gate electrode, and A lower portion extending from the upper portion into the undercut region, and Wherein the upper portion and the lower portion are integrally formed.
18. 18. The semiconductor device of claim 17, Wherein the first gate dielectric layer extends between the first gate electrode and the first gate spacer, the first gate dielectric layer being in contact with the side and top surfaces of the lower portion.
19. 19. The semiconductor device of claim 17, wherein the second gate dielectric layer extends between the second gate electrode and the second gate spacer, the second gate spacer being in contact with a top surface and side surfaces of the lower gate dielectric layer.
20. 20. A method of forming a semiconductor device, the method comprising: defining a first active region and a second active region on a substrate; forming a first gate electrode across the first active region and a second gate electrode across the second active region; Forming a first drain region in the first active region at a position adjacent to the first gate electrode, and forming a second drain region in the second active region at a position adjacent to the second gate electrode; forming a first gate spacer on a side surface of the first gate electrode; Forming a lower gate dielectric layer between the second active region and the second gate electrode, and Forming a second gate spacer on a side surface of the second gate electrode, Wherein the first gate spacer extends in an undercut region between the first active region and the first gate electrode, Wherein the first gate spacer comprises: An upper portion on a side surface of the first gate electrode, and A lower portion extending from the upper portion into the undercut region, and Wherein the upper portion and the lower portion are integrally formed.

Description

Semiconductor device including gate spacer Cross Reference to Related Applications The present application claims priority from korean patent application No.10-2020-0042140, entitled "Semiconductor Devices Including GATE SPACER", filed on 7 th month 4 in 2020, which is incorporated herein by reference in its entirety. Technical Field The present disclosure relates to semiconductor devices including gate spacers and methods of forming the same. Background With the trend of high integration of semiconductor devices, technologies using gate spacers and replacement gate electrodes have been developed. The shape of the gate spacer has a great influence on the process of forming the replacement gate electrode. Disclosure of Invention A semiconductor device according to an example embodiment of the present disclosure may include a first active region defined on a substrate. The first gate electrode may be disposed on the first active region across the first active region. The first drain region may be disposed in the first active region adjacent to the first gate electrode. The undercut region may be disposed between the first active region and the first gate electrode. The first gate spacer may be disposed on a side surface of the first gate electrode and may extend into the undercut region. A semiconductor device according to an exemplary embodiment of the present disclosure may include a first active region defined in a first region on a substrate. The first gate electrode may be disposed on the first active region across the first active region. The first drain region may be disposed in the first active region adjacent to the first gate electrode. The first gate spacer may be disposed on a side surface of the first gate electrode. The second active region may be defined in a second region on the substrate. The second gate electrode may be disposed on the second active region across the second active region, and may have a horizontal width different from that of the first gate electrode. The second drain region may be disposed in the second active region adjacent to the second gate electrode. The lower gate dielectric layer may be disposed between the second active region and the second gate electrode, and may have a smaller width than that of the second gate electrode. The second gate spacer may be disposed on a side surface of the second gate electrode and may extend in an undercut region between the second active region and the second gate electrode. The second gate spacer may be in contact with a side surface of the lower gate dielectric layer. A semiconductor device according to an exemplary embodiment of the present disclosure may include a first active region defined in a first region on a substrate. The first gate electrode may be disposed on the first active region across the first active region. The first gate dielectric layer may be disposed between the first active region and the first gate electrode. A pair of first drain regions may be disposed in the first active region at positions adjacent to opposite sides of the first gate electrode, and may be spaced apart from each other. The undercut region may be disposed between the first active region and the first gate electrode. The first gate spacer may be disposed on a side surface of the first gate electrode and may extend into the undercut region. The second active region may be defined in a second region on the substrate. The second gate electrode may be disposed on the second active region across the second active region, and may have a horizontal width greater than that of the first gate electrode. The second gate dielectric layer may be disposed between the second active region and the second gate electrode. A pair of second drain regions may be disposed in the second active region at positions adjacent to opposite sides of the second gate electrode, and may be spaced apart from each other. The lower gate dielectric layer may be disposed between the second active region and the second gate dielectric layer, and may have a horizontal width greater than that of the second gate electrode. The second gate spacer may be disposed on a side surface of the second gate electrode. The first active region may include a plurality of channel regions. Each of the plurality of channel regions may be in contact with the pair of first drain regions. The first gate electrode may surround a top surface, a side surface, and a bottom surface of at least one of the plurality of channel regions. The second gate electrode may be disposed on a top surface and a side surface of the second active region. The lower end of the second gate electrode may be disposed at a lower level than the upper end of the second active region. A method of forming a semiconductor device according to an example embodiment of the present disclosure may include defining a first active region and a second active region on a substrate. A first gate electrode may be formed on the first active r