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CN-113574801-B - Delay circuit and driving device

CN113574801BCN 113574801 BCN113574801 BCN 113574801BCN-113574801-B

Abstract

The delay circuit comprises at least one register, wherein the register is used for controlling one of the at least two branches to be connected in an on mode, so that the delay circuit generates delay corresponding to the connected branch. Since the slew rate is smaller as the delay of the input signal is larger, the slew rate of the input signal through any one of the at least two branches is different. The slew rate of the output signal can be adjusted by controlling one of the at least two branches to be connected through at least one register, so that the slew rate of the output signal can be compatible with different protocols or different modes under the same protocol.

Inventors

  • LI JIN

Assignees

  • 华为技术有限公司

Dates

Publication Date
20260508
Application Date
20190320

Claims (15)

  1. 1. A delay circuit, the delay circuit comprising: The MOS transistors comprise at least two branches, wherein the at least two branches are connected in parallel, each branch in the at least two branches has different time delays, and the number and/or the size of the MOS transistors included in each branch in the at least two branches are different, so that the at least two branches have different time delays; the delay circuit comprises at least one register, and the at least one register is used for controlling one branch of the at least two branches to be connected according to different protocols or different working modes of the same protocol, so that the delay circuit generates delay corresponding to the connected branch; the at least two branches comprise a first branch and a second branch, and the at least one register is used for controlling one branch of the first branch and the second branch to be connected; The first branch circuit comprises a first PMOS tube and a second PMOS tube, wherein the source electrode of the first PMOS tube is connected with a power supply voltage, the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, the grid electrode of the first PMOS tube is connected with an input signal, and the grid electrode of the second PMOS tube is connected with the input of the at least one register; The first branch circuit further comprises a first NMOS tube and a second NMOS tube, the source electrode of the first NMOS tube is grounded, the drain electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, the grid electrode of the first NMOS tube is connected with the input signal, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and the grid electrode of the second NMOS tube is connected with the input of the at least one register; The first branch circuit further comprises two PMOS pipes and two NMOS pipes, wherein the source electrode of one PMOS pipe is connected with the power supply voltage, the drain electrode of the other PMOS pipe is connected with the source electrode of the other PMOS pipe, the grid electrode of the other PMOS pipe is connected with the input signal, the source electrode of the other PMOS pipe is grounded, the drain electrode of the other NMOS pipe is connected with the source electrode of the other NMOS pipe, the grid electrode of the one NMOS pipe is connected with the input signal, the drain electrode of the other PMOS pipe is connected with the drain electrode of the other NMOS pipe, the grid electrode of the other NMOS pipe is connected with the input signal, and the grid electrodes of the first PMOS pipe and the first NMOS pipe are connected with the drain electrode of the other PMOS pipe; The second branch comprises a third PMOS tube and a fourth PMOS tube, the source electrode of the third PMOS tube is connected with a power supply voltage, the drain electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube, the grid electrode of the third PMOS tube is connected with the input signal, and the grid electrode of the fourth PMOS tube is connected with the input of the at least one register; The second branch circuit further comprises a third NMOS tube and a fourth NMOS tube, the source electrode of the third NMOS tube is grounded, the drain electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube, the grid electrode of the third NMOS tube is connected with the input signal, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the grid electrode of the fourth NMOS tube is connected with the input of the at least one register.
  2. 2. The delay circuit of claim 1 wherein the at least one register comprises a first register for controlling one of the first leg and the second leg to turn on.
  3. 3. The delay circuit of claim 2 wherein said first register comprises a first input and a second input, said first input and said second input being inverted, a gate of said second PMOS transistor being connected to said first input of said first register, a gate of said second NMOS transistor being connected to said second input of said first register.
  4. 4. The delay circuit of claim 3 wherein a gate of said fourth PMOS tube is connected to said second input of said first register and a gate of said fourth NMOS tube is connected to said first input of said first register.
  5. 5. The delay circuit of claim 4 wherein said first input of said first register is 0, said second input is 1, said second PMOS and said second NMOS are both open, said fourth PMOS and said fourth NMOS are both closed, said first leg is on; Or the first input of the first register is 1, the second input is 0, the second PMOS tube and the second NMOS tube are both closed, the fourth PMOS tube and the fourth NMOS tube are both opened, and the second branch is connected.
  6. 6. The delay circuit of claim 1 wherein the at least one register comprises a first register and a second register, the first register controlling the first leg and the second register controlling the second leg, the first leg being in communication with one of the second legs.
  7. 7. The delay circuit of claim 6 wherein the first register comprises a first input and a second input, the first input and the second input being inverted, a gate of the second PMOS transistor being connected to the first input of the first register, a gate of the second NMOS transistor being connected to the second input of the first register.
  8. 8. The delay circuit of claim 7 wherein the second register comprises a third input and a fourth input, the third input and the fourth input being inverted, a gate of the fourth PMOS transistor being connected to the third input of the second register, a gate of the fourth NMOS transistor being connected to the fourth input of the second register.
  9. 9. The delay circuit of claim 8 wherein the first branch is turned on when a first register controls the second PMOS and the second NMOS to both open and the second register controls the fourth PMOS and the fourth NMOS to both close; Or when the first register controls the second PMOS tube and the second NMOS tube to be closed and the second register controls the fourth PMOS tube and the fourth NMOS tube to be opened, the second branch is connected.
  10. 10. The delay circuit of claim 9 wherein the first input of the first register is 0, the second input is 1, the third input of the second register is 1, the fourth input is 0, the second PMOS and the second NMOS are both open, the fourth PMOS and the fourth NMOS are both closed, the first branch is open; Or the first input of the first register is 1, the second input is 0, the third input of the second register is 0, the fourth input is 1, the second PMOS tube and the second NMOS tube are closed, the fourth PMOS tube and the fourth NMOS tube are opened, and the second branch is connected.
  11. 11. A driving device, characterized in that the driving device comprises: A delay circuit and an N-stage driving circuit as claimed in any one of claims 1 to 10, N being an integer greater than 1; The output of the N-1 level delay circuit is respectively connected with the input of the N level delay circuit and the input of the N-1 level drive circuit; the output of the N-th stage delay circuit is connected with the input of the N-th stage drive circuit; N output signals of the 1 st-stage driving circuit to the N-stage driving circuit jointly form the output of the driving device; The driving circuit comprises at least one PMOS tube, at least one NMOS tube, a first resistor and a second resistor, wherein the at least one PMOS tube is connected with the first resistor in series, the grid electrode of the at least one PMOS tube is connected with the input signal, the at least one NMOS tube is connected with the second resistor in series, and the grid electrode of the at least one NMOS tube is connected with the input signal.
  12. 12. The driving device according to claim 11, wherein a delay between an output of the driving device and the input signal is related to at least one of a number of MOS transistors in the driving device, a size of a MOS transistor, a number of stages of the N-stage delay circuit and the N-stage driving circuit, a delay of a branch to which each of the N-stage delay circuits is turned on, or a delay of the N-stage driving circuit.
  13. 13. The drive of claim 12, wherein the delay between the output of the drive and the input signal comprises a delay of the N-stage delay circuit and a delay of the N-stage drive circuit, wherein the delay of the N-stage delay circuit is related to a number of stages of the N-stage delay circuit and a delay of a leg of each of the N-stage delay circuits that is on.
  14. 14. The drive of any one of claims 11 to 13, wherein a delay between an output of the drive and the input signal is a (T 1 +T 2 +……+T N )+T load , wherein a is a correction coefficient, T 1 is a delay of a first stage of the N stage of delay circuits, T 2 is a delay of a second stage of the N stage of delay circuits, T N is a delay of an nth stage of delay circuits of the N stage of delay circuits, and T load is a delay of the N stage of drive circuits.
  15. 15. The driving device according to any one of claims 11 to 13, wherein a delay between an output of the driving device and the input signal is a×n×t d +T load , wherein a is a correction coefficient, N is a number of stages of the N-stage delay circuit, T d is a delay of each of the N-stage delay circuits, and T load is a delay of the N-stage driving circuit.

Description

Delay circuit and driving device Technical Field The application relates to the field of electricity, in particular to a delay circuit and a driving device. Background In the field of data communication, when a circuit structure is designed, a circuit can be designed in a parallel mode or in a serial mode. The circuit designed by adopting the data parallel mode needs a plurality of transmission routes, the chip packages have more pins, and the circuit board needs complex layout. In the parallel system, since there are a plurality of lines, there are signal coupling and interference between signals between the plurality of lines, which affect the transmission speed and transmission distance of parallel transmission. Furthermore, parallel data transmission requires the transmission of a synchronous clock, which can occur when the lines are long. The circuit designed in a serial mode needs at least one pair of transmission lines and does not need to transmit synchronous clocks. Therefore, the serial data transmission mode is more suitable for a high-speed communication system. In a communication system, the larger the delay of a circuit output signal, the smaller the slew rate. In the prior art, an input signal can be delayed through a buffer (buffer), and a plurality of metal oxide semiconductor (metal oxide semiconductor, MOS) tubes are arranged in the buffer circuit and have a delay effect on the input signal. The number and the size of the MOS transistors in each buffer are determined. The delay of the input signal after passing through the buffer is determined, so the slew rate of the output signal after passing through the buffer circuit is determined, but different protocols or different working modes of the same protocol have different requirements on the slew rate of the circuit, so the compatibility of the circuit provided by the prior art to different protocols or different working modes under the same protocol is not high. Disclosure of Invention In view of this, the first aspect of the embodiment of the present application provides a delay circuit, which may include at least two branches, where the at least two branches are connected in parallel, and each of the at least two branches has a different delay, and the delay circuit includes at least one register for controlling one of the at least two branches to be turned on, so that the delay circuit generates a delay corresponding to the turned-on branch. Because each branch circuit has different delays, different delays can be provided by controlling different branch circuits to be connected through a register, the delay circuit provided by the embodiment of the application can provide different delays, which is equivalent to that an output signal can have a plurality of different slew rates, and the slew rate of the output signal can be compatible with different protocols or different modes under the same protocol by adjusting the slew rate of the output signal. Optionally, with reference to the first aspect, in a first possible implementation manner of the first aspect, the number and/or the size of MOS transistors included in each of the at least two branches are different, so that the at least two branches have different delays. In a first possible implementation manner of the first aspect, the number and/or the size of the MOS transistors included in each branch may be changed, so that each branch of the at least two branches has a different delay. Optionally, with reference to the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the at least one register includes a first register, and the at least two branches include a first branch and a second branch, and the first register is used for controlling one of the first branch and the second branch to be turned on. In a second possible implementation manner of the first aspect, only one register is needed to control one of the first branch and the second branch to be turned on, and only one register is used to reduce cost. Optionally, with reference to the second possible implementation manner of the first aspect, in three possible implementation manners of the first aspect, the first register includes a first input and a second input, the first input and the second input are inverted, the first branch includes a first PMOS tube and a second PMOS tube, a source electrode of the first PMOS tube is connected to a power supply voltage, a drain electrode of the first PMOS tube is connected to a source electrode of the second PMOS tube, a gate electrode of the first PMOS tube is connected to an input signal, a gate electrode of the second PMOS tube is connected to the first input of the first register, the first branch further includes a first NMOS tube and a second NMOS tube, a source electrode of the first NMOS tube is grounded, a drain electrode of the first NMOS tube is connected to a source electrode of the second NMOS tube