CN-113644881-B - Receiver front-end architecture for in-band carrier aggregation

Abstract

A receiver front-end architecture for in-band carrier aggregation is disclosed. In an exemplary embodiment, an apparatus includes a first transistor having a gate terminal receiving an input signal, a drain terminal outputting an amplified signal, and a source terminal connected to signal ground through a source degeneration inductor. The apparatus also includes a second transistor having a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to the first load. The apparatus further includes a third transistor having a gate terminal connected to the drain terminal of the first transistor, a drain terminal connected to the second load, and a source terminal connected to signal ground.

Inventors

• G. Rajandran
• G.S. SAHOTA
• R. kuma

Assignees

• 高通股份有限公司

Dates

Publication Date

20260505

Application Date

20150930

Priority Date

20141113

Claims (20)

1. 1. An electronic device, comprising: a first transistor having a gate terminal configured to receive an input signal, a drain terminal configured to output an amplified signal, and a source terminal connected to a signal ground through a source degeneration inductor; A second transistor having a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to a first signal path, and A third transistor having a gate terminal connected to the drain terminal of the first transistor, a drain terminal connected to a second signal path, and a source terminal connected to the signal ground, Wherein the drain terminal of the third transistor is selectively connected to the first signal path through a switch.
2. 2. The electronic device of claim 1, further comprising a fourth transistor having a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to the first signal path, the fourth transistor configured to conduct the same or a different amount of current than the second transistor.
3. 3. The electronic device of claim 2, the fourth transistor selectively enabled or biased by a control signal for DC coupling to control current to a first load connected to the first signal path.
4. 4. The electronic device of claim 1, further comprising one or more additional transistors having one or more gate terminals connected to the drain terminal of the first transistor, respectively, one or more drain terminals connected to one or more signal paths, respectively, and one or more source terminals connected to the signal ground.
5. 5. The electronic device of claim 4, the one or more drain terminals selectively connected to the one or more signal paths through one or more switches.
6. 6. The electronic device of claim 5, the one or more switches being selectively enabled by one or more control signals.
7. 7. The electronic device of claim 4, the drain terminal of the one or more additional transistors being selectively connected to the first signal path through one or more switches.
8. 8. The electronic device of claim 7, the one or more switches being selectively enabled by one or more control signals.
9. 9. The electronic device of claim 1, the second transistor being selectively enabled or biased for DC coupling by a control signal.
10. 10. The electronic device of claim 1, the drain terminal of the third transistor being selectively connected to the second signal path through a switch.
11. 11. The electronic device of claim 10, the switch selectively enabled or biased for DC coupling by a control signal.
12. 12. The electronic device of claim 4, wherein the first signal path connects the drain terminal of the second transistor to a first load, the second signal path connects the drain terminal of the third transistor to a second load, and the one or more signal paths respectively connect the drain terminals of the one or more additional transistors to one or more loads, wherein the first load comprises a main load, and the second load and the one or more loads comprise carrier aggregation loads.
13. 13. The electronic device of claim 4, wherein the first signal path comprises a main signal path and the second signal path and one or more signal paths comprise carrier aggregated signal paths.
14. 14. The electronic device of claim 1, the switch being selectively enabled by a control signal.
15. 15. The electronic device of claim 1, further comprising a controller to generate a control signal to selectively enable the second and third transistors or bias the second and third transistors for DC coupling.
16. 16. The electronic device of claim 1, configured to perform configurable amplification and routing of carrier aggregated signals in a receiver.
17. 17. The electronic device of claim 1, formed on an integrated circuit.
18. 18. The electronic device of claim 1, further comprising a further transistor having a gate terminal connected to the drain terminal of the third transistor, a drain terminal connected to a further signal path, and a source terminal connected to the signal ground.
19. 19. The electronic device of claim 18, the drain terminal of the further transistor being selectively connected to the first signal path through a switch.
20. 20. The electronic device of claim 19, the switch being selectively enabled by a control signal.

Description

Receiver front-end architecture for in-band carrier aggregation The application is a divisional application of an application patent application with the application number 201580061296.0 and the application name of 'receiver front end architecture for in-band carrier aggregation', wherein the application date is 2015, 09 and 30. Technical Field The present disclosure relates generally to electronics, and more particularly to configurable routing of radio frequency signals in wireless devices. Background A wireless device (e.g., a cellular telephone or a smart phone) in a wireless communication system may transmit and receive data for two-way communication. For example, the wireless device may be in an operating Frequency Division Duplex (FDD) system or in a Time Division Duplex (TDD) system. A wireless device may include a transmitter for data transmission and a receiver for data reception. For data transmission, the transmitter may modulate a Radio Frequency (RF) carrier signal with data to obtain a modulated RF signal, amplify and filter the modulated RF signal to obtain an amplified RF signal having an appropriate output power level, and transmit the amplified RF signal to the base station via the antenna. For data reception, the receiver may obtain a received RF signal via an antenna and may amplify, filter, and process the received RF signal to recover data transmitted by the base station. A wireless device may support operation over a wide frequency range. For example, a wireless device may operate in a Carrier Aggregation (CA) communication system, where the device includes a front end that receives a plurality of Downlink (DL) carrier signals over a wide frequency range. The front end operates to amplify the received carrier signals and route them to the appropriate demodulator for demodulation. Unfortunately, conventional front ends may utilize multiple amplifiers, each with a degeneration (degeneration) inductor. The large size of these inductors means that conventional front ends utilize significant circuit area. Furthermore, if amplifiers used to amplify multiple carrier signals are spread across multiple chips, it may be difficult to compensate for various gains and circuit routing losses that may be incurred. It is therefore desirable to have a front-end architecture in a carrier aggregation receiver that provides efficient amplification and routing of received signals. The front end should operate to maintain excellent linearity, provide compensation for gain and routing losses, and reduce or minimize circuit area requirements relative to conventional front ends. Drawings Fig. 1 illustrates an exemplary embodiment of a front-end architecture for use in a wireless device communicating within a wireless system. Fig. 2 illustrates three exemplary band groups in which the exemplary embodiment of the front-end architecture illustrated in fig. 1 may operate. Fig. 3 illustrates a receiver including an exemplary embodiment of a front-end architecture that provides configurable RF signal amplification and routing. Fig. 4 shows a detailed exemplary embodiment of the front-end architecture shown in fig. 3. Fig. 5 illustrates a detailed alternative exemplary embodiment of the front-end architecture illustrated in fig. 3. FIG. 6 illustrates an exemplary embodiment of a controller for use with the front end architecture shown in FIG. 4. Fig. 7 illustrates exemplary operations performed by an exemplary embodiment of a front-end architecture to provide RF signal amplification and routing in a receiver front-end. Fig. 8 illustrates an exemplary embodiment of a table showing control signal settings for various signal amplification and routing configurations for use with the front-end architecture shown in fig. 4 and 5. Fig. 9 illustrates an exemplary embodiment of an apparatus for RF signal amplification and routing in a carrier aggregation receiver. Detailed Description The detailed description set forth below is intended as a description of an exemplary design of the present disclosure and is not intended to represent the only design in which the present disclosure may be practiced. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other designs. The detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary designs of the present disclosure. It will be apparent to one skilled in the art that the exemplary designs described herein may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the novelty of the exemplary designs presented herein. Disclosed herein is a novel receiver front-end architecture that provides configurable RF signal amplification and routing in a device to demodulate multi