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CN-113671771-B - Preparation of silicon carbide and nitride structures on a carrier substrate

CN113671771BCN 113671771 BCN113671771 BCN 113671771BCN-113671771-B

Abstract

Methods, apparatus, and systems for forming semiconductor structures. A first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate is combined with a first oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate having the doped layer is etched using a photo-electrochemical etching process, wherein the doping level of the doped layer is such that the doped layer is removed and the silicon carbide layer in the silicon carbide substrate remains unetched. A semiconductor structure is formed using the silicon carbide layer and the group III nitride layer.

Inventors

  • S. J. Whiteley
  • D. Yap
  • E.H.Chen
  • D.M.Jin
  • T. D. Rudd

Assignees

  • 波音公司
  • 波音公司

Dates

Publication Date
20260421
Application Date
20210512
Priority Date
20200514

Claims (15)

  1. 1. A method for forming a semiconductor structure, the method comprising: Step (2600) forming a set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on a silicon carbide substrate (100, 1003), wherein the silicon carbide substrate (100, 1003) comprises doped layers (106, 904, 1302), and wherein the doped layers (106, 904, 1302) have doping levels such that the doped layers (106, 904, 1302) are etched using a photo-electrochemical etching process while other portions of the silicon carbide substrate (100, 1003) remain unetched; Step (2602) forming a first oxide layer over the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is located between the first oxide layer and the silicon carbide substrate (100, 1003); Step (2604) bonding the first oxide layer with a first oxide layer on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) located between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312); a step (2606) of grinding the silicon carbide substrate (100, 1003); Step (2608) stopping the grinding when reaching a part of the doped layers (106, 904, 1302) in the silicon carbide substrate (100, 1003); A step (2610) of etching the silicon carbide substrate (100, 1003) using the photoelectrochemical etching process such that the doped layer (106, 904, 1302) is removed and the silicon carbide device layer in the silicon carbide substrate (100, 1003) is left behind when the partially doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is exposed, and Step (2612) forms the semiconductor structure using the silicon carbide device layer and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).
  2. 2. The method of claim 1, wherein step (2604) is performed after etching the silicon carbide substrate (100, 1003).
  3. 3. The method of any of the preceding claims, wherein step (2604) is performed after etching a group III nitride layer of the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).
  4. 4. The method according to any of claims 1-2, wherein step (2604) is performed before etching the silicon carbide substrate (100, 1003).
  5. 5. The method according to any one of claims 1-2, wherein step (2604) comprises: A step (2700) of contacting a first surface of a first oxide layer on the group III-nitride layer with a second surface of the first oxide layer on the carrier substrate, wherein intermolecular interactions occur between the two first oxide layers, and Step (2702) anneals two first oxide layers while bringing the first surface into direct contact with the second surface to form an oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).
  6. 6. The method of any one of claims 1-2, wherein step (2610) comprises: One of a silicon face and a carbon face of the silicon carbide substrate (100, 1003) is etched using the photoelectrochemical etching process such that the doped layer (106, 904, 1302) is removed and the silicon carbide device layer in the silicon carbide substrate (100, 1003) remains when the partially doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is exposed.
  7. 7. The method of any of claims 1-2, wherein the doped layer (106, 904, 1302) is a sacrificial layer that enables formation of the silicon carbide device layer on a wafer, the silicon carbide device layer having at least one of a desired thickness uniformity or a desired level of optical performance, and/or wherein the semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, or a photon emitting quantum memory using point defects within the silicon carbide device layer.
  8. 8. The method of any of claims 1-2, wherein the silicon carbide device layer and the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are thin film layers, wherein the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) is one of a silicon carbide substrate (100, 1003), a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silicon dioxide substrate, an aluminum nitride substrate, and a gallium nitride substrate, and/or wherein the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) comprises at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and indium aluminum nitride (InAlGaN).
  9. 9. A method for forming a semiconductor structure, the method comprising: Step (2800) combining a first oxide layer located on a set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on a silicon carbide substrate (100, 1003) with a first oxide layer located on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204) located between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2310, 2312), wherein the silicon carbide substrate (100, 1003) has a doped layer (106, 904, 1302); Step (2082) etches the silicon carbide substrate (100, 1003) with the doped layer (106, 904, 1302) using a photo-electrochemical etching process, wherein the doping level of the doped layer (106, 904, 1302) is such that the doped layer (106, 904, 1302) is removed and the silicon carbide device layer in the silicon carbide substrate (100, 1003) remains unetched, and Step (2804) forms the semiconductor structure using the silicon carbide device layer and the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).
  10. 10. The method of claim 9, further comprising: Step (2606) of grinding the silicon carbide substrate (100, 1003) prior to etching the silicon carbide substrate (100, 1003); Step (2608) stopping grinding of the silicon carbide substrate (100, 1003) when reaching a part of the doped layers (106, 904, 1302) in the silicon carbide substrate (100, 1003) before etching the silicon carbide substrate (100, 1003); step (2600) forming the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on the silicon carbide substrate (100, 1003), and/or Step (2602) forms a first oxide layer over the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is located between the first oxide layer and the silicon carbide substrate (100, 1003).
  11. 11. The method according to any of claims 9-10, wherein step (2800) is performed after etching the silicon carbide substrate (100, 1003).
  12. 12. The method of any of claims 9-10, wherein step (2800) is performed after etching a group III nitride layer of the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).
  13. 13. The method according to any of claims 9-10, wherein step (2800) is performed before etching the silicon carbide substrate (100, 1003).
  14. 14. The method of any one of claims 9-10, wherein step (2800) includes: A step (2700) of contacting a first surface of a first oxide layer on the group III-nitride layer with a second surface of the first oxide layer on the carrier substrate, wherein intermolecular interactions occur between the two first oxide layers, and Step (2702) anneals two first oxide layers while bringing the first surface into direct contact with the second surface to form the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).
  15. 15. The method of any of claims 9-10, wherein the doped layer (106, 904, 1302) is a sacrificial layer that enables formation of a silicon carbide device layer on the wafer, the silicon carbide device layer having at least one of a desired thickness uniformity or a desired level of optical performance, wherein the semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, or a photon emitting quantum memory using point defects within the silicon carbide device layer, wherein the silicon carbide device layer and the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2100, 2212, 2310, 2312) are thin film layers, wherein the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2302, 2402) is at least one of a silicon carbide substrate (100, 1003), a silicon, an aluminum oxide substrate, a gallium oxide substrate, a silicon dioxide substrate, an aluminum nitride substrate, and/or wherein the group III nitride layer (200, 908, 1308, 1310, 1606, 2210, 2312) is a gallium nitride layer, and/or one of the group III nitride(s) comprises gallium nitride (200, 2216, aluminum nitride, 2210, aluminum nitride, and/or group III, gallium nitride).

Description

Preparation of silicon carbide and nitride structures on a carrier substrate Technical Field The present disclosure relates generally to semiconductors, and in particular, to methods for forming semiconductor structures, and in particular, to forming silicon carbide and nitride structures on a carrier substrate. Background Silicon carbide and group III nitrides, such as gallium nitride, are ideal semiconductors for signal processing and quantum applications. These materials have a wide bandgap and a larger nonlinear optical coefficient than 3 eV compared to other materials currently used for low-loss photonics and on-chip nonlinear optics, such as silicon, silicon dioxide, and silicon nitride materials. Silicon carbide (SiC) is a semiconductor material that contains silicon and carbon. Silicon carbide may be used in devices for quantum information processing and other purposes. For example, a color center in a silicon carbide structure may be used to provide an optical reading indicative of its electron spin state. Each color center is a qubit in quantum computing. The state of a qubit may be a logical "0", a logical "1", or a superposition of both states. For example, the color center may be incorporated into a photonic device, such as a microcavity for a waveguide element. Manufacturing devices on silicon carbide structures can be challenging. For example, devices formed using thin films with silicon carbide and group III nitrides may be more difficult to manufacture than desired than other materials such as silicon. Thin film devices include one or more thin film layers, where the thickness of the thin film layers may be on the order of nanometers to a few micrometers. The quality of thin film devices using silicon carbide and group III nitrides formed on a wafer may not be as good as desired compared to materials such as silicon. Accordingly, it is desirable to have a method and apparatus that addresses at least some of the problems discussed above, as well as other possible problems. For example, it is desirable to have a method and apparatus that overcomes the technical problems associated with forming silicon carbide and group III nitride structures of desired quality. Disclosure of Invention Embodiments of the present disclosure provide a method for forming a semiconductor structure. A set of group III nitride layers are formed on a silicon carbide substrate. The silicon carbide substrate includes a doped layer. The doped layer has a doping level such that the doped layer is etched using a photo-electrochemical etching process while other portions of the silicon carbide substrate remain unetched. A first oxide layer is formed over the set of group III nitride layers. The group III-nitride layer is located between the first oxide layer and the silicon carbide substrate. The first oxide layer is combined with a second oxide layer on the carrier substrate to form an oxide layer between the carrier substrate and the group III-nitride layer. The silicon carbide substrate is ground. The milling is stopped when a portion of the doped layer in the silicon carbide substrate is exposed. The silicon carbide substrate is etched using photoelectrochemical etching such that the doped layer is removed and the silicon carbide layer in the silicon carbide substrate remains when the partially doped layer in the silicon carbide substrate is exposed. A semiconductor structure is formed using the silicon carbide layer and the group III nitride layer. Another embodiment of the present disclosure provides a method for forming a semiconductor structure. A first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate is combined with a second oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate having the doped layer is etched using a photo-electrochemical etching process, wherein the doping level of the doped layer is such that the doped layer is removed and the silicon carbide layer in the silicon carbide substrate remains unetched. A semiconductor structure is formed using the silicon carbide layer and the group III nitride layer. Yet another embodiment of the present disclosure provides a product management system including a manufacturing apparatus and a control system. The control system controls the fabrication apparatus to combine a first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate with a second oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate having the doped layer is etched using a photo-electrochemical etching process. The doping level of the doped layer is such that the doped layer is