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CN-113678374-B - Frequency detector for measuring and tuning the frequency of a controlled oscillator

CN113678374BCN 113678374 BCN113678374 BCN 113678374BCN-113678374-B

Abstract

A frequency detector (200) and methods therein for measuring and tuning the frequency of a controlled oscillator are disclosed. The frequency detector (200) comprises a pulse generator (210) for generating sampling pulses, sampling circuitry (220) for sampling the output state of the controlled oscillator (180), and a digital processing unit (230). The sampling circuitry (220) is configured to sub-sample the output state of the controlled oscillator (180) at two or more sampling frequencies, and all sampling frequencies are lower than the frequency of the controlled oscillator. The digital processing unit (230) is configured to calculate a frequency offset of the oscillator based on the sampled state and to generate a control signal to tune the frequency of the oscillator based on the frequency offset.

Inventors

  • H. Sjorand
  • R. Kasri

Assignees

  • 瑞典爱立信有限公司

Dates

Publication Date
20260505
Application Date
20190411

Claims (20)

  1. 1. A frequency detector (200) for measuring and tuning the frequency of a controlled oscillator (180), comprising: A pulse generator (210) for generating sampling pulses; sampling circuitry (220) for sampling an output state of the controlled oscillator (180), and A digital processing unit (230), wherein, The sampling circuitry (220) is configured to sub-sample the output state of the controlled oscillator (180) at two or more sampling frequencies, and all sampling frequencies are lower than the frequency of the controlled oscillator; the digital processing unit (230) is configured to calculate a frequency offset of the oscillator based on the sampled state, and to generate a control signal to tune the frequency of the oscillator based on the frequency offset; Wherein the sampling circuitry (220) comprises two or more sampling circuits configured to simultaneously sub-sample the output state of the controlled oscillator at different sampling frequencies.
  2. 2. The frequency detector (200) of claim 1, wherein the sampling circuitry (220) is configured to sub-sample the output state of the controlled oscillator at a first frequency during a first period of time and to sub-sample the output state of the controlled oscillator at a second frequency during a second period of time.
  3. 3. A frequency detector (300) for measuring and tuning the frequency of a controlled oscillator, comprising: A pulse generator (310) for generating sampling pulses; a multi-stage divider (340) connected to the output of the controlled oscillator; sampling circuitry (320) for sampling the output state from each stage of the divider, and A digital processing unit (330), wherein, -The sampling circuitry (320) is configured to sub-sample the output state of the frequency divider at a sampling frequency lower than the frequency of the controlled oscillator; the digital processing unit (330) is configured to calculate a frequency offset of the oscillator based on the sampled state, and to generate a control signal to tune the frequency of the oscillator based on the frequency offset; Wherein the sampling circuitry (220) comprises two or more sampling circuits configured to simultaneously sub-sample the output state of the controlled oscillator at different sampling frequencies.
  4. 4. The frequency detector (300) of claim 3, wherein the sampling circuitry is further configured to sub-sample an output state of the controlled oscillator.
  5. 5. Frequency generation circuitry (900) comprising a controlled oscillator (180) and a frequency detector (200, 300) according to any of claims 1 to 4.
  6. 6. The frequency generation circuitry (900) of claim 5, wherein the controlled oscillator (180) is a multi-stage ring oscillator and the sampling circuitry (320) is configured to sub-sample the state of the ring oscillator at the output of each stage.
  7. 7. An electronic device (1000) comprising frequency generation circuitry (900) according to any of claims 5 to 6.
  8. 8. The electronic device (1000) of claim 7, comprising a receiver, a transmitter, and a transceiver.
  9. 9. A method for measuring and tuning the frequency of a controlled oscillator, comprising: Sub-sampling (410) the state of the controlled oscillator at a sampling frequency that is lower than the frequency of the controlled oscillator; calculating (420) a state difference between adjacent pairs of sampled states; estimating (430) a frequency offset based on the state difference; Generating (440) a control signal based on the frequency offset, and Tuning (450) the frequency of the controlled oscillator based on the control signal; wherein sub-sampling the state of the controlled oscillator comprises sub-sampling the output of the controlled oscillator at two sampling frequencies simultaneously.
  10. 10. The method of claim 9, wherein sub-sampling the state of the controlled oscillator comprises sub-sampling the output of the controlled oscillator one at a time at two sampling frequencies.
  11. 11. The method of claim 9, wherein the output of the controlled oscillator is coupled to a multi-stage divider, and wherein sub-sampling the state of the controlled oscillator comprises sub-sampling the output of the multi-stage divider coupled to the controlled oscillator.
  12. 12. The method of claim 9, wherein calculating the state difference between each adjacent pair of states comprises: Converting each sampled state into a state number based on its position in the state sequence, and The previous state number is subtracted from the current state number.
  13. 13. The method of claim 9, further comprising wrapping around some state differences by: if the state difference is higher than the total number of states divided by 2, then a number representing the total number of states is subtracted from the state difference, or If the state difference is below the negative of the total number of states divided by 2, the number representing the total number of states is added to the state difference.
  14. 14. The method of claim 9, further comprising correcting or skipping some of the state differences.
  15. 15. The method of claim 9, further comprising averaging the state differences of the time periods of the first few samples to obtain an initial average of the state differences.
  16. 16. The method of claim 15, further comprising skipping some of the state differences based on comparing state differences to the initial average.
  17. 17. The method of claim 16, wherein skipped state differences are those state differences whose state differences are less than the initial average value minus 1 and greater than the initial average value plus 1.
  18. 18. The method of claim 16, wherein skipped state differences are those not included within a range of [ initial average-max_state_difference+|initial average|, initial average + max_state_difference- |initial average| ], wherein max_state_difference is a maximum value of the state differences, and|initial average|is an absolute value of the initial average.
  19. 19. The method of claim 9, further comprising averaging the state differences over a period of time to obtain a state difference average.
  20. 20. The method of claim 9, wherein estimating a frequency offset based on the state difference is performed using a look-up table containing a list of state difference averages with corresponding frequency offsets.

Description

Frequency detector for measuring and tuning the frequency of a controlled oscillator Technical Field Embodiments herein relate to a frequency detector for measuring and tuning the frequency of a controlled oscillator. In particular, they relate to frequency detectors with sub-sampling frequency detection, frequency generation circuitry including the frequency detectors, and electronic devices (such as receivers, transmitters, and transceivers) including the frequency generation circuitry. Background In wireless communication systems, the trend to support devices with ultra-low power consumption is very strong. These devices may be small sensor nodes where the battery should be used for years, or where energy harvesting is used to achieve battery-less operation. When a wireless communication system is to communicate with such a device, the receiver must be operated in the device. In order to achieve a limited response time, the receiver must be operated periodically. Then, the power consumption of the receiver must be limited. Therefore, special ultra low power receivers, so-called wake-up receivers, are often used. The wake-up receiver has limited performance and is only able to detect the presence of wake-up requests. When such a request is present, the primary receiver with higher performance and higher power is activated to be able to receive the actual communication data. To achieve ultra low power consumption, e.g. below 100 uW, the wake-up receiver is based on amplitude detection of the on-off keying signal. Thus, the use of a power-hungry Phase Locked Loop (PLL) to generate an accurate Local Oscillator (LO) signal can be avoided. However, only moderate filtering can be achieved before amplitude detection, and immunity is essentially limited to that achievable by the correlation of pseudo-random noise (PN) sequences. Wake-up receivers are susceptible to interference due to the limited amount of filtering prior to amplitude detection. All interference and noise entering the amplitude detector, which has an amplitude modulation in the same frequency range as the wake-up request signal, will mask the desired signal. It should be understood here that the same frequency does not mean that interference exists only on the same frequency channel. In contrast, since the ability to filter out signals adjacent in frequency to the wake-up signal is limited, it should be appreciated that signals transmitted in adjacent channels and even potentially further away will effectively have the same detrimental effects as co-channel interfering signals. In order to be able to effectively filter out adjacent interference, the frequency generation in the wake-up receiver must have a high accuracy and thus consume a lot of energy. In addition, the amplitude detector is also highly nonlinear, and therefore produces a very small output signal for a weak input signal. Assuming that the amplitude detector has a quadratic characteristic for small input signals, this means that for every 10 dB drops in input signal level, the signal-to-noise ratio drops by 20 dB, which becomes very disadvantageous soon when the detector input has been moderately disturbed. Thus, more filtering before amplitude detection is necessary to achieve wake-up receivers with high immunity, which however increases power consumption. Disclosure of Invention It is therefore an object of embodiments herein to provide a frequency generation circuitry with improved performance in terms of accuracy and power consumption. According to one aspect of embodiments herein, this object is achieved by a frequency detector for measuring and tuning the frequency of a controlled oscillator. The frequency detector comprises a pulse generator for generating sampling pulses, sampling circuitry for sampling the output state of the controlled oscillator, and a digital processing unit. The sampling circuitry is configured to sub-sample the output state of the controlled oscillator at two or more sampling frequencies, and all sampling frequencies are lower than the frequency of the controlled oscillator. The digital processing unit is configured to calculate a frequency offset of the oscillator based on the sampled state and to generate a control signal to tune the frequency of the oscillator based on the frequency offset. According to one aspect of embodiments herein, this object is achieved by a frequency detector for measuring and tuning the frequency of a controlled oscillator. The frequency detector comprises a pulse generator for generating sampling pulses, a multi-stage frequency divider connected to the output of the controlled oscillator, sampling circuitry for sampling the output states from each stage of the frequency divider, and a digital processing unit. The sampling circuitry is configured to sub-sample the output state of the frequency divider at a sampling frequency that is lower than the frequency of the controlled oscillator. The digital processing unit is confi