CN-113690213-B - Packaged multichip semiconductor device

Abstract

A semiconductor package is provided that includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bonding pad on the first semiconductor chip, a first bonding insulating layer on the first semiconductor chip and the first molding layer and surrounding the first bonding pad, a second bonding pad in direct contact with the first bonding pad, a second bonding insulating layer surrounding the second bonding pad, and a second semiconductor chip on the second bonding pad and the second bonding insulating layer.

Inventors

• Li Hezai
• LI ZHONGHAO
• JIN ZHIXUN
• JIN TAIXUN
• Pu Xiangtian
• Xue Zhenjing
• LI XIANGXUN

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20210225

Priority Date

20200518

Claims (18)

1. 1. A packaged semiconductor device, the semiconductor device comprising: A first connection structure; The first semiconductor chip is positioned on the upper surface of the first connecting structure and comprises a semiconductor substrate, a through substrate via hole and a first chip pad; a first molding layer positioned on an upper surface of the first connection structure and at least partially surrounding the first semiconductor chip; a first bonding pad on the first semiconductor chip; A first bond insulating layer at least partially surrounding the first bond pad; a second bonding pad directly contacting the first bonding pad; a second bonding insulating layer at least partially surrounding the second bonding pad, and A second semiconductor chip on the second bonding pad and the second bonding insulating layer, Wherein the first chip pad is located between the through substrate via and the first bonding pad and is in direct contact with the first bonding pad, and Wherein the through-substrate via extends through the semiconductor substrate to electrically connect to the first bond pad through the first chip pad.
2. 2. The semiconductor device according to claim 1, wherein the second bonding insulating layer directly contacts the first bonding insulating layer.
3. 3. The semiconductor device according to claim 1, further comprising: a connection member penetrating the first molding layer; A third bonding pad positioned on the connection member and at least partially surrounded by the first bonding insulating layer, and And a fourth bond pad in direct contact with the third bond pad and at least partially surrounded by the second bond insulating layer.
4. 4. The semiconductor device of claim 1, wherein the first semiconductor chip further comprises a semiconductor device on the semiconductor substrate.
5. 5. The semiconductor device according to claim 4, wherein the first semiconductor chip further comprises: the second chip pad is located between the through substrate via and the first connection structure.
6. 6. The semiconductor device of claim 1, wherein the first semiconductor chip further comprises a semiconductor device adjacent to a surface of the semiconductor substrate.
7. 7. The semiconductor device according to claim 1, further comprising: And an external connection terminal on a lower surface of the first connection structure.
8. 8. The semiconductor device of claim 1, wherein a side surface of the first connection structure is coplanar with a side surface of the first molding layer.
9. 9. The semiconductor device of claim 1, wherein a side surface of the second semiconductor chip is coplanar with a side surface of the first molding layer.
10. 10. The semiconductor device of claim 1, further comprising a second molding layer positioned on the second bonding insulating layer and at least partially surrounding the second semiconductor chip.
11. 11. A packaged semiconductor device, the semiconductor device comprising: a redistribution structure; Solder bumps on the first surface of the redistribution structure; the semiconductor device comprises a redistribution structure, a first semiconductor chip, an upper chip pad, a through substrate via and a through substrate via, wherein the first semiconductor chip is positioned on a second surface of the redistribution structure and comprises a semiconductor substrate, a lower chip pad is positioned on the lower surface of the semiconductor substrate, the upper chip pad is positioned on the upper surface of the semiconductor substrate, and the through substrate via is positioned in the semiconductor substrate and extends between the lower chip pad and the upper chip pad; a first molding layer located on the second surface of the redistribution structure and at least partially surrounding the first semiconductor chip; a first bonding pad on the upper die pad of the first semiconductor die; a first bonding insulating layer on the upper surface of the first semiconductor chip and the upper surface of the first molding layer and at least partially surrounding the first bonding pad; a second bonding pad contacting the first bonding pad; a second bonding insulating layer contacting the first bonding insulating layer and at least partially surrounding the second bonding pad, and A second semiconductor chip on the second bonding pad and the second bonding insulating layer, Wherein the upper chip pad is in direct contact with the first bonding pad, and Wherein the through-substrate via extends through the semiconductor substrate to electrically connect to the first bond pad through the upper die pad.
12. 12. The semiconductor device according to claim 11, further comprising: A third semiconductor chip located on the second surface of the redistribution structure and at least partially surrounded by the first molding layer; a third bonding pad positioned on the upper surface of the third semiconductor chip and at least partially surrounded by the first bonding insulating layer, and And a fourth bond pad in direct contact with the third bond pad and at least partially surrounded by the second bond insulating layer.
13. 13. The semiconductor device according to claim 11, wherein the first and second bonding insulating layers each comprise a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and combinations thereof.
14. 14. The semiconductor device of claim 11, wherein a coefficient of thermal expansion of the first molding layer is in a range of 0 ppm/°c to 10 ppm/°c.
15. 15. A packaged semiconductor device, the semiconductor device comprising: A connection structure; The first semiconductor chip is positioned on the upper surface of the connecting structure and comprises a semiconductor substrate, a through substrate via hole and a first chip pad; a first bonding pad on the first semiconductor chip; A first bonding insulating layer extending over the first semiconductor chip and at least partially surrounding the first bonding pad; a second bonding pad directly contacting the first bonding pad; a second bond insulating layer at least partially surrounding the second bond pad; a second semiconductor chip on the second bonding pad and the second bonding insulating layer, and A first molding layer positioned on the second bonding insulating layer and at least partially surrounding the second semiconductor chip, Wherein the first chip pad is located between the through substrate via and the first bonding pad and is in direct contact with the first bonding pad, and Wherein the through-substrate via extends through the semiconductor substrate to electrically connect to the first bond pad through the first chip pad.
16. 16. The semiconductor device of claim 15, wherein a side surface of the first semiconductor chip is coplanar with a side surface of the first molding layer.
17. 17. The semiconductor device of claim 15, further comprising a second molding layer extending between the connection structure and the first bonding insulating layer and at least partially surrounding the first semiconductor chip.
18. 18. The semiconductor device according to claim 15, further comprising: a third bonding pad on the first semiconductor chip and at least partially surrounded by the first bonding insulating layer; A fourth bonding pad directly contacting the third bonding pad and at least partially surrounded by the second bonding insulating layer, and A third semiconductor chip is positioned on the fourth bond pad and the second bond insulating layer and is at least partially surrounded by the first mold layer.

Description

Packaged multichip semiconductor device The present application claims the benefit of korean patent application No. 10-2020-0059328 filed on 5/18/2020, the disclosure of which is hereby incorporated by reference. Technical Field The inventive concept relates to packaged semiconductor devices, and more particularly, to packaged multi-chip semiconductor devices. Background High performance and compact electronic devices are continually being demanded. Due to these demands, a semiconductor package including a plurality of semiconductor chips has been developed. For example, a plurality of semiconductor chips may be stacked in a vertical direction, thereby reducing a layout area of a semiconductor package and providing a multi-functional and/or high-performance semiconductor package. Disclosure of Invention The inventive concept provides an integrated circuit package in which a plurality of semiconductor chips are connected via bonding without any bump (e.g., solder ball), and a method of manufacturing the same. According to an aspect of the inventive concept, there is provided a packaged semiconductor device including a first connection structure, a first semiconductor chip, a first molding layer positioned on an upper surface of the first connection structure and surrounding the first semiconductor chip, a first bonding pad positioned on the first semiconductor chip, a first bonding insulating layer positioned on the first semiconductor chip and the first molding layer and surrounding the first bonding pad, a second bonding pad directly contacting the first bonding pad, a second bonding insulating layer surrounding the second bonding pad, and a second semiconductor chip positioned on the second bonding pad and the second bonding insulating layer. According to another aspect of the inventive concept, there is provided a packaged semiconductor device including a redistribution structure, solder bumps on a lower surface of the redistribution structure, and a first semiconductor chip positioned on an upper surface of the redistribution structure. The first semiconductor chip includes a substrate, a lower die pad on a lower surface of the substrate, an upper die pad on an upper surface of the substrate, and a through-substrate via (TSV) extending between the lower die pad and the upper die pad by penetrating the substrate. A first molding layer is also provided, the first molding layer being positioned on the upper surface of the redistribution structure and at least partially surrounding the first semiconductor chip. The first bonding pad is disposed on an upper die pad of the first semiconductor die. A first bond insulating layer is provided that is positioned over the upper surface of the first semiconductor chip and the upper surface of the first molding layer (and at least partially surrounds the first bond pad). A second bond pad is provided, the second bond pad directly contacting the first bond pad. A second bonding insulating layer is provided, the second bonding insulating layer directly contacting the first bonding insulating layer and surrounding the second bonding pad. And the second semiconductor chip is disposed on the second bonding pad and the second bonding insulating layer. According to another aspect of the inventive concept, there is provided a packaged semiconductor device including a connection structure, a first semiconductor chip on an upper surface of the connection structure, a first bonding pad on the first semiconductor chip, a first bonding insulating layer positioned on the first semiconductor chip and at least partially surrounding the first bonding pad, a second bonding pad directly contacting the first bonding pad, and a second bonding insulating layer at least partially surrounding the second bonding pad. The second semiconductor chip is further disposed on the second bonding pad and the second bonding insulating layer. A first molding layer is provided that is positioned over the second bonding insulating layer and at least partially surrounds the second semiconductor chip. According to another aspect of the inventive concept, there is provided a packaged semiconductor device including a package substrate, an interposer on the package substrate, first and second bond pads on the interposer, and a first bond insulating layer positioned on the interposer and at least partially surrounding the first and second bond pads. A third bond pad is also provided and a fourth bond pad is provided, the third bond pad directly contacting the first bond pad and the fourth bond pad directly contacting the second bond pad. A second bond insulating layer is provided that at least partially surrounds the third bond pad and the fourth bond pad. The first semiconductor chip is disposed on the second bonding insulating layer and the third bonding pad, and the second semiconductor chip is disposed on the second bonding insulating layer and the fourth bonding pad. A molding layer is provided that is po