CN-113764029-B - Apparatus and method for parallel generation of syndrome and partial coefficient information

Abstract

An error correction apparatus according to the technical idea of the present disclosure includes a syndrome generating circuit configured to receive data and generate a plurality of syndromes for the data, a partial coefficient generating circuit configured to generate partial coefficient information related to a part of coefficients of an error location polynomial by using the data while generating the plurality of syndromes, an error location determining circuit configured to determine the coefficients of the error location polynomial based on the plurality of syndromes and the partial coefficient information and obtain a location of an error in the data by using the error location polynomial, and an error correcting circuit configured to correct the error in the data according to the location of the error.

Inventors

• Li Enai
• Li Qizhun
• SONG YINGJIE
• LI MINGKUI
• HUANG SHIXIA

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20210602

Priority Date

20200603

Claims (20)

1. 1. An error correction apparatus comprising: A syndrome generation circuit configured to receive data and generate a plurality of syndromes for the data; a partial coefficient generation circuit configured to receive the data and generate partial coefficient information on a part of a first coefficient among coefficients of an error location polynomial by using the data while the syndrome generation circuit generates the plurality of syndromes; an error location polynomial generation circuit configured to receive the partial coefficient information and the plurality of syndromes, determine the first coefficient based on the partial coefficient information and the plurality of syndromes, determine a second coefficient other than the first coefficient among coefficients of the error location polynomial based on the plurality of syndromes, and generate the error location polynomial based on the first coefficient, the second coefficient, and the plurality of syndromes; An error location determination circuit configured to obtain a location of an error in the data by using the error location polynomial, and An error correction circuit configured to correct the error in the data according to a position of the error.
2. 2. The error correction apparatus according to claim 1, wherein the partial coefficient generation circuit generates, as the partial coefficient information, information on the first coefficient including a nonlinear operation among coefficients of the error location polynomial while the plurality of syndromes are generated.
3. 3. The error correction apparatus according to claim 2, wherein the partial coefficient generation circuit generates, as the partial coefficient information, information on the first coefficient including a power value of a target syndrome among coefficients of the error location polynomial while the plurality of syndromes are generated.
4. 4. The error correction apparatus according to claim 3, wherein the partial coefficient generation circuit generates the partial coefficient information by performing a first summation operation among double summation operations for calculating a power value of the target syndrome while the plurality of syndromes are generated.
5. 5. The error correction apparatus according to claim 4, wherein the power value of the target syndrome is calculated by performing a second summation operation among the double summation operations using the partial coefficient information.
6. 6. The error correction apparatus according to claim 1, wherein the partial coefficient generation circuit generates the partial coefficient information using a syndrome term that has been generated among a plurality of syndrome terms within a target syndrome while the plurality of syndromes are generated.
7. 7. The error correction apparatus according to claim 6, wherein the syndrome generation circuit sends the generated syndrome term among a plurality of syndrome terms within the target syndrome to the partial coefficient generation circuit, wherein the target syndrome is a syndrome among the plurality of syndromes.
8. 8. An error correction method, comprising: Reading data from the memory cell array; generating a plurality of syndromes for the data; Generating partial coefficient information related to a portion of a first coefficient among coefficients of an error location polynomial using the data while generating the plurality of syndromes; determining the first coefficient based on the partial coefficient information and the plurality of syndromes; determining a second coefficient other than the first coefficient among coefficients of the error location polynomial based on the plurality of syndromes, Generating the error location polynomial based on the first coefficient, the second coefficient, and the plurality of syndromes; obtaining the location of errors in the data by using the error location polynomial, and The error in the data is corrected based on the location of the error.
9. 9. The error correction method of claim 8, wherein generating partial coefficient information relating to a portion of the first coefficients of the error location polynomial using the data while generating the plurality of syndromes comprises: Information on the first coefficient including a nonlinear operation among coefficients of the error location polynomial is generated as the partial coefficient information.
10. 10. The error correction method according to claim 9, wherein the partial coefficient information is information on the first coefficient including a power value of a target syndrome among coefficients of the error location polynomial.
11. 11. The error correction method according to claim 10, wherein the partial coefficient information is generated by a first summation operation among double summation operations for calculating a power value of the target syndrome.
12. 12. The error correction method according to claim 11, wherein, A power value of the target syndrome is calculated by performing a second summation operation among the double summation operations using the partial coefficient information.
13. 13. The error correction method of claim 8, wherein generating partial coefficient information relating to a portion of the first coefficients of the error location polynomial using the data while generating the plurality of syndromes comprises: The partial coefficient information is generated using a syndrome term that has been generated among a plurality of syndrome terms within a target syndrome while the plurality of syndromes are generated.
14. 14. A volatile memory device, comprising: A memory cell array including a plurality of memory cells, and An error correction engine configured to correct data read from the memory cell array, Wherein the error correction engine comprises: a syndrome generating circuit configured to generate a plurality of syndromes using data read from the memory cell array; a partial coefficient generation circuit configured to generate partial coefficient information on a part of a first coefficient among coefficients of an error location polynomial by using the data while the syndrome generation circuit generates the plurality of syndromes; an error location polynomial generation circuit configured to receive the partial coefficient information and the plurality of syndromes, determine the first coefficient based on the partial coefficient information and the plurality of syndromes, determine a second coefficient other than the first coefficient among coefficients of the error location polynomial based on the plurality of syndromes, and generate the error location polynomial based on the first coefficient, the second coefficient, and the plurality of syndromes; An error location determination circuit configured to obtain a location of an error in the data by using the error location polynomial, and An error correction circuit configured to correct the error in the data based on a location of the error.
15. 15. The volatile memory device according to claim 14, wherein the partial coefficient generation circuit generates, as the partial coefficient information, information on the first coefficient including a nonlinear operation among coefficients of the error location polynomial while the plurality of syndromes are generated.
16. 16. The volatile memory device according to claim 15, wherein the partial coefficient generation circuit generates, as the partial coefficient information, information on the first coefficient including a power value of a target syndrome among coefficients of the error location polynomial while the plurality of syndromes are generated.
17. 17. The volatile storage device according to claim 16, wherein the partial coefficient generation circuit generates the partial coefficient information by performing a first summation operation among double summation operations for calculating a power value of the target syndrome while the plurality of syndromes are generated.
18. 18. The volatile storage device of claim 17, wherein the power value of the target syndrome is calculated by performing a second summation operation among the double summation operations using the partial coefficient information.
19. 19. The volatile memory device according to claim 14, wherein the partial coefficient generation circuit generates the partial coefficient information using a syndrome term that has been generated among a plurality of syndrome terms within a target syndrome while the plurality of syndromes are generated.
20. 20. The volatile storage device of claim 19, wherein the syndrome generation circuit sends the generated syndrome term among a plurality of syndrome terms within the target syndrome to the partial coefficient generation circuit, wherein the target syndrome is a syndrome among the plurality of syndromes.

Description

Apparatus and method for parallel generation of syndrome and partial coefficient information Cross Reference to Related Applications The present application claims the benefit of korean patent application No.10-2020-0067163 filed at korean intellectual property office on 3 th month 6 of 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field The present disclosure herein relates to an error correction apparatus and an error correction method for generating a syndrome and partial coefficient information in parallel. Background The error correction decoder may perform Error Correction Coding (ECC) to correct error bits in the information data. As communication speeds increase and data throughput increases, the number of erroneous bits in the information data may increase. Due to the increase of error bits, the error correction delay required from when the error correction decoder receives information data until the error correction decoder outputs correction data may be prolonged. Disclosure of Invention The problem solved by the technical idea of the present disclosure is to reduce error correction delay by generating a partial coefficient and a syndrome of an error position equation in parallel. An error correction apparatus according to an aspect of the present disclosure includes a syndrome generating circuit configured to receive data and generate a plurality of syndromes for the data, a partial coefficient generating circuit configured to generate partial coefficient information related to a part of coefficients of an error location polynomial by using the data while generating the plurality of syndromes, an error location determining circuit configured to determine the coefficients of the error location polynomial based on the plurality of syndromes and the partial coefficient information and obtain a location of an error in the data by using the error location polynomial, and an error correcting circuit configured to correct the error in the data according to the location of the error. An error correction method according to aspects of the present disclosure includes reading data from a memory cell array, generating a plurality of syndromes for the data, generating partial coefficient information related to a portion of coefficients of an error location polynomial using the data while generating the plurality of syndromes, determining coefficients of the error location polynomial based on the plurality of syndromes and the partial coefficient information, and obtaining a location of an error in the data by using the error location polynomial, and correcting the error in the data based on the location of the error. A volatile memory device according to aspects of the present disclosure includes a memory cell array including a plurality of memory cells, and an error correction engine configured to correct data read from the memory cell array, wherein the error correction engine includes a syndrome generation circuit configured to generate a plurality of syndromes using the data read from the memory cell array, a partial coefficient generation circuit configured to generate partial coefficient information related to a part of coefficients of an error location polynomial while generating the plurality of syndromes, an error location determination circuit configured to determine the coefficients of the error location polynomial based on the plurality of syndromes and the partial coefficient information and obtain a location of an error in the data by using the error location polynomial, and an error correction circuit configured to correct the error in the data based on the location of the error. Drawings Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which like reference numerals identify like elements. In the drawings: FIG. 1 is a block diagram illustrating an error correction apparatus according to an exemplary embodiment of the present disclosure; FIG. 2 is a flowchart illustrating an error correction method according to an exemplary embodiment of the present disclosure; FIG. 3 is a graph illustrating delay for error correction according to an exemplary embodiment of the present disclosure; FIG. 4 is a diagram illustrating a syndrome generation circuit according to an exemplary embodiment of the present disclosure; FIG. 5 is a diagram for describing an error correction polynomial generation circuit in accordance with an exemplary embodiment of this disclosure; Fig. 6 is a diagram illustrating a partial coefficient generation circuit according to an exemplary embodiment of the present disclosure; FIG. 7 is a diagram for describing an error correction device according to an exemplary embodiment of the present disclosure; Fig. 8 is a diagram illustrating a partial coefficient generation circuit according to an exemplary embodiment of the present di