CN-113874944-B - Method and apparatus for self-trimming memory devices

Abstract

The present disclosure relates to an integrated memory device comprising-a memory cell array with decoding and sensing circuitry, -a memory controller, -read and write circuitry associated with the sensing circuitry, -a logic circuitry portion in the read and write circuitry comprising at least one logic element receiving a data stream on a data input and a clock signal on a clock input, -at least one programmable or trimmable delay element or circuit upstream of the data input or the clock input for self-trimming the internal timing of the at least one logic element by temporally aligning the clock signal and/or the data stream. The present disclosure further relates to a method for setting operating parameters of an integrated circuit, in particular for self-tuning internal timing of said integrated circuit.

Inventors

• A Troya
• A. Monte Delta

Assignees

• 美光科技公司

Dates

Publication Date

20260512

Application Date

20190531

Claims (20)

1. 1. A method for self-trimming an integrated circuit, comprising: In response to receiving an indication of an operating temperature change or a reference voltage change, looking up in a look-up table operating parameters corresponding to the current operating temperature and reference voltage, and In response to not finding the operating parameters corresponding to the current operating temperature and reference voltage: Setting the operating parameters of the integrated circuit (200) for self-trimming internal timing of the integrated circuit, the integrated circuit comprising a circuit portion receiving a data stream on a data input and a clock signal on a clock input, Wherein setting the operating parameters includes time aligning at least one of the clock signal or the data stream by inserting an upstream programmable or trimmable delay element or circuit (170, 180, 190) before one or both of the inputs, an The operating parameters relative to the current operating temperature and reference voltage are recorded in the look-up table.
2. 2. The method of claim 1, further comprising establishing operating conditions when the integrated circuit is factory new.
3. 3. The method of claim 1, wherein temporally aligning comprises inserting a programmable or trimmable delay element or circuit (190) upstream of the clock input to modify a relative distance between the data stream and a valid or leading edge of the clock signal.
4. 4. The method of claim 1, wherein temporally aligning comprises inserting a programmable or trimmable delay element or circuit (170, 180) upstream of the data input to modify a relative distance between the data stream and an active or leading edge of the clock signal.
5. 5. The method of claim 1, wherein the self-trimming of the internal timing of the integrated circuit is performed automatically.
6. 6. The method of claim 1, wherein temporally aligning comprises adjusting the upstream programmable or trimmable delay element or circuit to reset a timing difference between a sampling clock signal and a sampling data signal.
7. 7. The method of claim 1, wherein temporally aligning comprises adjusting a set time interval of the circuit portion.
8. 8. The method of claim 1, wherein aligning in time phase comprises adjusting a hold time interval of the circuit portion.
9. 9. The method of claim 1, wherein temporally aligning comprises adjusting the upstream programmable or trimmable delay element or circuit by a configuration signal.
10. 10. The method of claim 1, wherein temporally aligning comprises adjusting the upstream programmable or trimmable delay element or circuit by a delay chain.
11. 11. A method for self-trimming an integrated circuit, comprising: In response to receiving an indication of an operating temperature change or a reference voltage change, looking up in a look-up table operating parameters corresponding to the current operating temperature and reference voltage, and In response to not finding the operating parameters corresponding to the current operating temperature and reference voltage: Setting the operating parameters of the integrated circuit (200) for self-trimming internal timing of the integrated circuit, the integrated circuit comprising a circuit portion receiving a data stream on a data input and a clock signal on a clock input, Wherein setting the operating parameter comprises performing a tuning phase of at least one of a set time or a hold time by varying a relative time distance between the data stream received by a data input terminal and a valid edge of the clock signal by inserting a programmable or trimmable delay element or circuit (170, 180, 190), an The operating parameters relative to the current operating temperature and reference voltage are recorded in the look-up table.
12. 12. The method of claim 11, wherein performing the tuning phase comprises adjusting the programmable or trimmable delay element or circuit upstream of the clock input.
13. 13. The method of claim 11, wherein performing the tuning phase comprises adjusting the programmable or trimmable delay element or circuit upstream of the data input.
14. 14. The method of claim 11, wherein the tuning phase is performed automatically.
15. 15. The method of claim 11, further comprising establishing an operating parameter when the integrated circuit is factory new.
16. 16. The method of claim 11, comprising adjusting the programmable or trimmable delay element or circuit by a configuration signal.
17. 17. The method of claim 11, wherein the programmable or trimmable delay element or circuit is implemented by a delay chain.
18. 18. An integrated memory device, comprising: an array of memory cells having decoding and sensing circuitry; A memory controller; read and write circuitry associated with the sense circuitry; A logic circuit portion (150) in the read and write circuitry including logic elements that receive a data stream on a data input and a clock signal on a clock input, an A programmable or trimmable delay element or circuit (170, 180, 190) upstream of the data input or the clock input, and A trimming block including a first input indicative of an operating temperature and a second input indicative of a reference voltage; Wherein in response to receiving an indication of an operating temperature change or a reference voltage change, the integrated memory device is configured to: looking up the self-trimming operation parameters corresponding to the current operation temperature and the reference voltage in a lookup table, and In response to not finding the self-trimming operating parameter corresponding to the current operating temperature and reference voltage, causing the programmable or trimmable delay element or circuit to: Self-fine tuning the internal timing of the logic element by temporally aligning at least one of the clock signal or the data stream, and The self-trimming operating parameters relative to the indicated operating temperature and reference voltage are recorded in the look-up table.
19. 19. The memory device of claim 18, wherein the programmable or trimmable delay element or circuit (190) is inserted upstream of a clock signal path relative to the clock input.
20. 20. The memory device of claim 18, wherein the programmable or trimmable delay element or circuit (170, 180) is inserted upstream of a data flow path relative to the data input.

Description

Method and apparatus for self-trimming memory devices Technical Field The present disclosure relates to a method for setting operating parameters of an integrated circuit. More particularly, the present disclosure relates to a method for self-trimming operating parameters and internal timing of an integrated memory device. The present disclosure further relates to a non-volatile memory device having self-trimming capability in a wide temperature range application and a wide voltage range application. Background One of the main problems in the operation of integrated circuits is to guarantee functionality in all process extensions, supply and temperature variations. For example, any synchronization input addressed to the integrated circuit has the appropriate set and hold time specifications with respect to the clock input. The set time S is the amount of time (or time interval) that data received at the synchronous input of the simple flip-flop circuit D must remain stable before reaching the active edge of the clock signal to allow the circuit to capture such data well. Similarly, the hold time H is the amount of time (or time interval) that the data received at the synchronous input of the simple flip-flop circuit D must remain stable after reaching the active edge of the clock signal. The set and hold parameters S and H must be set appropriately in order for the integrated circuit to function properly. However, setting and maintaining are opposite parameters, in the sense better explained below, a high temperature typically slows down both intervals and a low temperature faster them, so both parameters will move correspondingly over time. Another parameter is given by the sum of two intervals s+h=mpw that should remain stable before and after the clock input changes. This interval MPW has a minimum value that allows normal operation, but this value may be even longer, as the signal may remain stable waiting for sampling and subsequent changes. In any event, violations of set and hold timing may not only generate a single fault condition, but even generate some serious faults, such as metastability of flip-flop outputs, that are indeterminate and cannot recover unless reset or power down and power up are forced. Integrated circuits are designed and simulated in view of the above problems, but for some applications, for example in the presence of large variations in power supply, temperature and process ranges, it is not possible to guarantee performance and functionality within a specified range. Some tests and trimming are done at the factory in an attempt to overcome possible process expansion, however, this common practice is time consuming because it must be performed on each individual IC, in other words per die. Disclosure of Invention In one aspect the application provides a method for setting an operating parameter of an integrated circuit, in particular for self-trimming the internal timing of said integrated circuit, said integrated circuit comprising a circuit portion receiving a data stream on a data input and a clock signal on a clock input, said method comprising aligning said clock signal and/or said data stream in time by inserting an upstream programmable or trimmable delay element or circuit before one or both of said inputs. In a further aspect the application provides a method for setting an operating parameter of an integrated circuit, in particular for self-trimming an internal timing of said integrated circuit, said integrated circuit comprising at least one circuit portion receiving a data stream at least on a data input and a clock signal at a clock input, said method comprising performing a tuning phase of a set time and/or a hold time by inserting a programmable or trimmable delay element or circuit to change a relative time distance between said data stream received by said data input and a valid edge of said clock signal. In another aspect, the present application provides an integrated memory device comprising an array of memory cells having decoding and sensing circuitry, a memory controller, read and write circuitry associated with the sensing circuitry, a logic circuitry portion in the read and write circuitry comprising at least one logic element receiving a data stream on a data input and a clock signal on a clock input, at least one programmable or trimmable delay element or circuit upstream of the data input or the clock input for self-trimming internal timing of the at least one logic element by temporally aligning the clock signal and/or the data stream. In another aspect, the present application provides an integrated memory device structured to communicate with a host device or system-on-chip over a communication channel having respective pads, comprising an array of memory cells having decoding and sensing circuitry, a memory controller, an output buffer coupled to the array of memory cells and comprising a selectable final output stage coupled to the pads, at lea