CN-113906508-B - Method for checking an erase phase of a memory device

Abstract

The present disclosure relates to a non-volatile memory device including at least one array of memory cells and associated decoding and sensing circuitry and a memory controller, and a method for checking an erase phase of the non-volatile device, the method comprising performing a dynamic erase operation of at least one memory block, storing at least an internal block variable and/or a known pattern of the dynamic erase operation in a dummy row.

Inventors

• A Troya
• A. Monte Delta

Assignees

• 美光科技公司

Dates

Publication Date

20260512

Application Date

20190531

Claims (20)

1. 1. A non-volatile memory device, comprising: A memory cell array, comprising: Multiple memory blocks A plurality of dummy rows corresponding to each respective memory block of the plurality of memory blocks, wherein each dummy row: Associated with a first address space that is located outside of a second address space of the respective memory block, and Configured to store internal block variables and specific patterns associated with the erase phase, and A controller coupled to the array of memory cells, and configured for each dummy row of the plurality of dummy rows to: determining whether the particular pattern is stored in the dummy row in response to power up of the array of memory cells, wherein determining that the particular pattern is not stored in the dummy row indicates an incomplete erase of the respective memory block, and In response to determining that the particular pattern is not stored in the dummy row, the erase phase is performed on the respective memory block.
2. 2. The non-volatile memory device of claim 1, wherein the internal block variable indicates a parameter of performing the erase phase on the respective memory block.
3. 3. The non-volatile memory device of claim 2, wherein the parameters of the erase phase comprise an erase pulse and a target voltage applied to the respective memory block associated with the erase phase.
4. 4. The non-volatile memory device of claim 1, wherein the plurality of memory blocks comprises a sub-array of the array of memory cells.
5. 5. A system, comprising: A host device; A non-volatile memory device coupled to the host device and comprising an array of memory cells and a controller coupled to the array of memory cells, wherein the array of memory cells comprises: a plurality of memory blocks; A plurality of dummy rows corresponding to each respective memory block of the plurality of memory blocks, wherein each dummy row: Associated with a first address space that is located outside of a second address space of the respective memory block, and Configured to store internal block variables and specific patterns associated with the erase phase, and Wherein the controller is configured for each dummy row of the plurality of dummy rows to: determining whether the particular pattern is stored in the dummy row in response to power up of the array of memory cells, wherein determining that the particular pattern is not stored in the dummy row indicates an incomplete erase of the respective memory block, and In response to determining that the particular pattern is not stored in the dummy row, the erase phase is performed on the respective memory block.
6. 6. The system of claim 5, wherein the controller is further configured to retrieve the internal block variable from the dummy row, wherein the internal block variable is associated with the erase phase previously performed on the respective memory block.
7. 7. The system of claim 6, wherein the controller is further configured to initiate execution of the erase phase on the respective memory block in response to retrieval of the internal block variable.
8. 8. The system of claim 5, wherein the dummy row is disposed in another one of the plurality of memory blocks or in a dedicated memory portion of the array of memory cells.
9. 9. The system of claim 5, wherein the internal block variable indicates a parameter of performing the erase phase on the respective memory block.
10. 10. The system of claim 9, wherein the parameters of the erase phase include an erase pulse and a target voltage applied to the respective memory block associated with the erase phase.
11. 11. The system of claim 5, wherein the plurality of memory blocks comprises a sub-array of the array of memory cells.
12. 12. A method, comprising: performing an erase phase on a memory block of a memory cell array of a non-volatile memory device; Storing an internal block variable associated with the erase phase and a particular pattern in a dummy row corresponding to the memory block prior to power-up of the memory cell array, wherein the dummy row is associated with a first address space that is outside of a second address space of a respective memory block; after the array of memory cells is powered up, determining whether the particular pattern is stored in the dummy row, wherein determining that the particular pattern is not stored in the dummy row indicates an incomplete erase of the respective memory block, and In response to determining that the particular pattern is not stored in the dummy row, the erase phase is performed on the respective memory block.
13. 13. The method of claim 12, wherein performing the erase phase comprises performing a dynamic erase operation on the respective memory block.
14. 14. The method of claim 13, further comprising invalidating content of the dummy row prior to performing the dynamic erase operation.
15. 15. The method of claim 12, wherein storing the internal block variables comprises storing parameters that perform the erase phase on the respective memory block.
16. 16. The method of claim 12, wherein storing the internal block variable comprises storing data indicative of an erase pulse and a target voltage applied to the respective memory block associated with performing the erase phase.
17. 17. The method of claim 12, further comprising retrieving the internal block variable from the dummy row, wherein the internal block variable is associated with the erase phase previously performed on the respective memory block.
18. 18. The method of claim 17, further comprising initiating the erase phase performed on the respective memory block in response to retrieving the internal block variable.
19. 19. The method of claim 18, wherein initiating execution of the erase phase comprises restoring the respective memory block.
20. 20. A method for erasing a non-volatile memory device, the method comprising: performing a dynamic erase operation of a memory block of the memory cell array; Storing an internal block variable of the dynamic erase operation in a dummy row prior to power-up of the memory cell array, wherein the dummy row is associated with a first address space that is located outside a second address space of the memory block; storing a known pattern in the dummy row prior to powering up the memory cell array; After the array of memory cells is powered up, determining whether the known pattern is stored in the dummy row, wherein determining that the known pattern is not stored in the dummy row indicates an incomplete erase of the memory block, and In response to determining that the known pattern is not stored in the dummy row, the dynamic erase operation is performed on the memory block.

Description

Method for checking an erase phase of a memory device Technical Field The present disclosure relates generally to memory devices and, more particularly, to methods for setting operating parameters of integrated memory circuits. More specifically, the present disclosure relates to methods for self-trimming operating parameters of a memory device and for checking an erase phase of the memory device. Background Memory devices are well known in the electronics arts to store digital information and allow access to the digital information. In general, different classes of semiconductor memory devices may be incorporated into more complex systems including non-volatile memory components as well as volatile memory components, such as into so-called systems-on-a-chip (SoC) in which the above memory components are embedded. However, today, the demands of automotive applications on real-time operating systems require that socs continuously increase their performance and efficiency, and known solutions no longer meet these demands. Nonvolatile memory can provide persistent data by still retaining stored data when not powered and can include NAND flash memory or NOR flash memory, and the like. NAND flash also has reduced erase and write times and requires less chip area per cell, thus allowing for greater storage density and lower cost per bit than NOR flash. An important feature of flash memory is the fact that it can be erased in blocks, rather than one byte at a time. However, one key drawback of flash memory is that it can only undergo a relatively small number of write and erase cycles in a particular block. Flash memory devices may include large arrays of memory cells, often organized into rows and columns, for storing data. Individual memory cells and/or ranges of memory cells are addressable by their rows and columns. When the memory array is addressed, there may be one or more address translation layers to translate, for example, between logical addresses utilized by the host device (i.e., soC) and physical addresses corresponding to the locations in the memory array. Although unusual, the address information provided to the memory device on its command/address bus may still be compromised due to errors, so that internal operations (e.g., read operations, write operations, erase operations, etc.) of the memory device may be performed on physical addresses that are different from the physical addresses targeted by the host device or the controller of the memory device. Thus, there is a need for a way to verify that a memory operation has been performed at an expected address, and the present disclosure focuses on a method of checking the correctness of the read phase. Disclosure of Invention In one aspect, the present disclosure relates to a non-volatile memory device including at least one memory cell array and associated decoding and sensing circuitry and a memory controller, wherein the memory array includes a plurality of memory blocks, at least one dummy row for each block, the dummy row being located outside an address space of each block for storing at least an internal block variable and at least a known pattern of an erase phase. In one aspect, the present disclosure relates to a system including a host device, a nonvolatile memory device coupled to the host device and including at least one array of memory cells and associated decoding and sensing circuitry and a memory controller, a plurality of memory blocks in the array of memory cells, at least one dummy row for each block located outside an address space of each block for storing at least an internal block variable and at least one known pattern of an erase phase. In another aspect, the present disclosure relates to a method for checking an erase operation of a non-volatile memory device including at least one array of memory cells and associated decoding and sensing circuitry and a memory controller, the method comprising performing an erase phase of a memory block, storing at least an internal block variable and at least a known pattern of the erase phase in a dummy row associated with the memory block. In another aspect, the present disclosure relates to a method for erasing a non-volatile memory device including at least one array of memory cells and associated decoding and sensing circuitry and a memory controller, the method comprising performing a dynamic erase operation of at least one memory block, storing at least an internal block variable of the dynamic erase operation in a dummy row, storing at least one known pattern in the dummy row. Drawings FIG. 1 shows a schematic diagram of a system including a memory component associated with a controller exchanging data, address and control signals with a memory device; FIG. 2 is a schematic diagram of a memory assembly according to the present disclosure; FIG. 3 is a schematic layout of an example of a memory component according to an embodiment of the present disclosure; FIG. 4 is a schemati