CN-113921480-B - Semiconductor package including semiconductor chip and dummy pad

Abstract

The semiconductor package includes a semiconductor chip on a package substrate, and a dummy pad disposed between the semiconductor chips and overlapping at least a portion of the semiconductor chips. The dummy pad is disposed on the package substrate and in a space between the package substrate and the semiconductor chip.

Inventors

• Cui Yinjing

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20210514

Priority Date

20200709

Claims (20)

1. 1. A semiconductor package, comprising: Packaging a substrate; A first semiconductor chip, a second semiconductor chip, and a third semiconductor chip on the package substrate, and A dummy pad laterally disposed between the first, second and third semiconductor chips to overlap at least a portion of the first, second and third semiconductor chips, Wherein the dummy pads are disposed on the package substrate and in a space between the package substrate and the first, second, and third semiconductor chips.
2. 2. The semiconductor package of claim 1, further comprising: And a molding member filling a space between the package substrate and the first, second and third semiconductor chips to cover a top surface of the dummy pad.
3. 3. The semiconductor package of claim 2, wherein the molding member extends in a T-shape from the top surface of the dummy pad.
4. 4. The semiconductor package of claim 1, further comprising: An underfill filling a space between the package substrate and the first, second and third semiconductor chips, covering a portion of the top surface of the dummy pad and covering the side surface of the dummy pad, and And a molding member covering another portion of the top surface of the dummy pad.
5. 5. The semiconductor package according to claim 1, wherein the second semiconductor chip and the third semiconductor chip are arranged in parallel along one side of the first semiconductor chip, The dummy pad has a lateral width greater than a separation distance between the first semiconductor chip and any one of the second semiconductor chip and the third semiconductor chip, and The dummy pad has a longitudinal width greater than a separation distance between the second semiconductor chip and the third semiconductor chip.
6. 6. The semiconductor package of claim 5, wherein the dummy pad overlaps the one side of the first semiconductor chip, overlaps an edge of the second semiconductor chip opposite the one side of the first semiconductor chip, and overlaps an edge of the third semiconductor chip opposite the one side of the first semiconductor chip.
7. 7. The semiconductor package of claim 1, further comprising: an insulating film including at least one of silicon oxide and silicon nitride disposed between the package substrate and the dummy pad.
8. 8. The semiconductor package of claim 1, wherein the package substrate comprises an interposer configured to provide electrical connection with at least one of the first, second, and third semiconductor chips.
9. 9. The semiconductor package of claim 1, wherein the dummy pad comprises a conductive metal material and is electrically isolated from the package substrate, the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip.
10. 10. The semiconductor package of claim 9, wherein the dummy pad has at least one of a flat plate shape, a stripe shape, and a matrix shape.
11. 11. A semiconductor package, comprising: a redistribution structure; at least three semiconductor chips on the redistribution structure; A dummy pad between the redistribution structure and the at least three semiconductor chips, and And a molding member filling a space between the at least three semiconductor chips such that the dummy pad overlaps at least a portion of each of the at least three semiconductor chips, and covering at least a portion of a top surface of the dummy pad.
12. 12. The semiconductor package of claim 11, wherein a width of the dummy pad is greater than a separation distance between any two of the at least three semiconductor chips.
13. 13. The semiconductor package of claim 11, wherein a bottom surface of each of the at least three semiconductor chips contacts the molding member, and The bottom surface of the dummy pad contacts an insulating film formed on the redistribution structure and including at least one of silicon oxide and silicon nitride.
14. 14. The semiconductor package of claim 11, wherein the dummy pads are electrically isolated.
15. 15. The semiconductor package of claim 11, wherein one of the at least three semiconductor chips has a stacked structure including a plurality of slices, and Another semiconductor chip of the at least three semiconductor chips has a single-layer structure.
16. 16. A semiconductor package, comprising: An insert; a semiconductor chip including a memory chip, a logic chip, and a dummy chip adjacently disposed on the interposer; A dummy pad disposed on the interposer and between the interposer and the semiconductor chip, wherein the dummy pad comprises a metal material; a molding member covering the bottom surface and the side surface of the semiconductor chip, wherein the molding member covers the top surface and the side surface of the dummy pad, and Solder bumps, adhered to the bottom surface of the interposer, Wherein the dummy pad overlaps at least a portion of each of the semiconductor chips.
17. 17. The semiconductor package of claim 16, wherein the dummy pad overlaps a side of the logic chip and overlaps an edge of each of the memory chip and the dummy chip.
18. 18. The semiconductor package of claim 17, wherein a first planar area of the dummy pad overlapping the logic chip is greater than each of a second planar area of the dummy pad overlapping the memory chip and a third planar area of the dummy pad overlapping the dummy chip.
19. 19. The semiconductor package of claim 16, wherein the memory chip is a high bandwidth memory chip and is a stacked structure comprising a plurality of slices.
20. 20. The semiconductor package of claim 16, wherein a width of the dummy pad is greater than a maximum distance separating the semiconductor chips.

Description

Semiconductor package including semiconductor chip and dummy pad Cross Reference to Related Applications The present application claims the benefit of korean patent application No.10-2020-0084940, filed on the korean intellectual property office at 7/9/2020, the subject matter of which is incorporated herein by reference. Technical Field The present inventive concept relates generally to semiconductor packages, and more particularly, to a semiconductor package called a System In Package (SiP), in which a single semiconductor package includes different types of semiconductor chips. Background There is a continuing increase in demand for portable devices in the electronics market. As a result, miniaturization and weight reduction of constituent components within electronic products have become important design driving forces. There are various methods to miniaturize and lighten electronic components. For example, a semiconductor package mounted in an electronic assembly may provide high capacity data processing, thereby reducing the overall volume of the semiconductor package. Semiconductor chips mounted in semiconductor packages may be densely or highly integrated within a single package. In this way, various SiP techniques can be applied to efficiently arrange (or layout) a plurality of semiconductor chips within a semiconductor package. Disclosure of Invention Embodiments of the inventive concept provide a semiconductor package including a dummy pad that can prevent cracks in a molding member, thereby effectively protecting different types of semiconductor chips facing each other in a limited structure provided by the semiconductor package. However, embodiments of the inventive concept may provide other benefits and technical objects, which will be apparent to those of ordinary skill in the art after considering the following description. According to one aspect of the inventive concept, there is provided a semiconductor package including a package substrate, first, second and third semiconductor chips on the package substrate, and dummy pads laterally disposed between the first, second and third semiconductor chips to overlap at least a portion of the first, second and third semiconductor chips, wherein the dummy pads are disposed on the package substrate and in spaces between the package substrate and the first, second and third semiconductor chips. According to one aspect of the inventive concept, there is provided a semiconductor package including a redistribution structure, at least three semiconductor chips on the redistribution structure, a dummy pad between the redistribution structure and the at least three semiconductor chips, and a molding member filling a space between the at least three semiconductor chips such that the dummy pad overlaps at least a portion of each of the at least three semiconductor chips, and the molding member covers at least a portion of a top surface of the dummy pad. According to one aspect of the inventive concept, there is provided a semiconductor package including an interposer, a semiconductor chip including a memory chip, a logic chip, and a dummy chip adjacently disposed on the interposer, a dummy pad disposed on the interposer and between the interposer and the semiconductor chip, wherein the dummy pad includes a metal material, a molding member covering a bottom surface and a side surface of the semiconductor chip, wherein the molding member covers a top surface and a side surface of the dummy pad, and a solder bump adhered to the bottom surface of the interposer, wherein the dummy pad overlaps at least a portion of each of the semiconductor chips. Drawings Examples of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: fig. 1 is a plan (or top) view of a semiconductor package according to an embodiment of the inventive concept; FIG. 2 is a cross-sectional view taken along line X-X' of FIG. 1; Fig. 3, 4 and 5 are respective enlarged sectional views of portion III of fig. 1; fig. 6, 7 and 8 are respective plan views of a semiconductor package according to an embodiment of the inventive concept; Fig. 9, 10, 11, 12, 13 and 14 (collectively, "fig. 9-14") are respective cross-sectional views taken along line X-X' of fig. 1, according to an embodiment of the inventive concept, and Fig. 15 is a block diagram illustrating a semiconductor package according to an embodiment of the inventive concept. Detailed Description Throughout the written description and drawings, like reference numbers and designations are used to refer to like or similar elements and/or features. Throughout the written description, certain geometric terms may be used to emphasize relative relationships between elements, components, and/or features for particular embodiments of the inventive concepts. Those skilled in the art will recognize that such geometric terms are relative in nature, are arbit