CN-113936609-B - Gate clock generator and display device

Abstract

The invention discloses a gate clock generator and a display device. The gate clock generator of the display device includes a carry clock generator that sequentially generates N carry clock signals (N is an integer of 2 or more) based on carry on and off clock signals, a scan clock generator that generates N scan clock signals based on scan on and off clock signals, and a sense clock generator that generates N sense clock signals based on sense on and off clock signals. In the multi-clock mode, during a turn-on interval of a kth carry clock signal (K is an integer of 1 or more and N or less), the scan clock generator outputs a kth scan clock signal having a number of pulses corresponding to a number of pulses of the scan turn-on clock signal, and the sense clock generator outputs a kth sense clock signal having a number of pulses corresponding to a number of pulses of the sense turn-on clock signal.

Inventors

• CHENG SHIDE
• LI DAZHI
• LI XIANGXIAN

Assignees

• 三星显示有限公司

Dates

Publication Date

20260505

Application Date

20210508

Priority Date

20200714

Claims (10)

1. 1. A gate clock generator which generates a gate clock signal for a gate driver of a display device, the gate clock generator comprising: a carry clock generator that sequentially generates N carry clock signals based on a carry on clock signal and a carry off clock signal, N being an integer of 2 or more; A scan clock generator for generating N scan clock signals based on the scan on clock signal and the scan off clock signal, and A sense clock generator generating N sense clock signals based on the sense on clock signal and the sense off clock signal, In the multiple clock mode, during a conduction interval of a kth one of the N carry clock signals, the scan clock generator outputs, as a kth one of the N scan clock signals, the kth one of the pulses having a number corresponding to a number of pulses of the scan conduction clock signal in the conduction interval of the kth one of the carry clock signals, and the sense clock generator outputs, as a kth one of the N sense clock signals, the kth sense clock signal having a number of pulses corresponding to a number of pulses of the sense conduction clock signal in the conduction interval of the kth one of the carry clock signals, K being an integer of 1 or more and N or less.
2. 2. The gate clock generator of claim 1, wherein the gate clock generator comprises a gate clock generator, In the multi-clock mode, the carry clock generator supplies the N carry clock signals to the scan clock generator and the sense clock generator.
3. 3. The gate clock generator of claim 2, wherein the gate clock generator comprises a gate clock generator, In the multi-clock mode, the scan clock generator changes the kth scan clock signal to an on level in response to each pulse of the scan on clock signal and changes the kth scan clock signal to an off level in response to each pulse of the scan off clock signal during the on interval of the kth carry clock signal, In the multi-clock mode, the sense clock generator changes the kth sense clock signal to the on level in response to each pulse of the sense on clock signal and changes the kth sense clock signal to the off level in response to each pulse of the sense off clock signal during the on interval of the kth carry clock signal.
4. 4. The gate clock generator of claim 1, wherein the gate clock generator comprises a gate clock generator, The carry clock generator includes: A carry mode selection block determining an operation mode of the gate clock generator and generating a mode signal representing the determined operation mode; A carry pulse generator block sequentially generating the N carry clock signals based on the carry on clock signal and the carry off clock signal and providing the N carry clock signals to the scan clock generator and the sense clock generator in response to the mode signal representing the multi-clock mode, and And a carry level shifter block adjusting voltage levels of the N carry clock signals to voltage levels suitable for a gate driver and supplying the N carry clock signals to the gate driver.
5. 5. The gate clock generator of claim 1, wherein the gate clock generator comprises a gate clock generator, The scan clock generator includes: A scan mode selection block determining an operation mode of the gate clock generator and generating a mode signal representing the determined operation mode; A scan pulse generator block generating the N scan clock signals based on the N carry clock signals, the scan on clock signals, and the scan off clock signals in response to the mode signals representing the multiple clock modes, and generating the N scan clock signals based on the scan on clock signals and the scan off clock signals in response to the mode signals representing the different operation modes from the multiple clock modes, and And a scan level shifter block adjusting voltage levels of the N scan clock signals to voltage levels suitable for a gate driver and supplying the N scan clock signals to the gate driver.
6. 6. The gate clock generator of claim 1, wherein the gate clock generator comprises a gate clock generator, The sense clock generator includes: A sensing mode selection block determining an operation mode of the gate clock generator and generating a mode signal representing the determined operation mode; a sense pulse generator block generating the N sense clock signals based on the N carry clock signals, the sense on clock signals, and the sense off clock signals in response to the mode signals representing the multiple clock modes, and generating the N sense clock signals based on the sense on clock signals and the sense off clock signals in response to the mode signals representing the different operation modes from the multiple clock modes, and And a sensing level shifter block adjusting voltage levels of the N sensing clock signals to voltage levels suitable for a gate driver and providing the N sensing clock signals to the gate driver.
7. 7. The gate clock generator of claim 1, wherein the gate clock generator comprises a gate clock generator, In the multi-clock mode, the carry clock generator provides a multi-sense enable signal to the scan clock generator and the sense clock generator.
8. 8. The gate clock generator of claim 7, wherein the gate clock generator comprises a gate clock generator, In the multi-clock mode, the scan clock generator changes a first scan clock signal of the N scan clock signals to an on level in response to each pulse of the scan on clock signal and changes the first scan clock signal to an off level in response to each pulse of the scan off clock signal during a first on interval of the multi-sense enable signal, changes a second scan clock signal of the N scan clock signals to the on level in response to each pulse of the scan on clock signal and changes the second scan clock signal to the off level in response to each pulse of the scan off clock signal during a second on interval of the multi-sense enable signal, In the multi-clock mode, the sense clock generator changes a first sense clock signal of the N sense clock signals to the on level in response to each pulse of the sense on clock signal and changes the first sense clock signal to the off level in response to each pulse of the sense off clock signal during the first on interval of the multi-sense enable signal, changes a second sense clock signal of the N sense clock signals to the on level in response to each pulse of the sense on clock signal and changes the second sense clock signal to the off level in response to each pulse of the sense off clock signal during the second on interval of the multi-sense enable signal.
9. 9. The gate clock generator of claim 1, wherein the gate clock generator comprises a gate clock generator, The carry clock generator includes: A carry mode selection block determining an operation mode of the gate clock generator and generating a mode signal representing the determined operation mode; a carry pulse generator block sequentially generating the N carry clock signals based on the carry on clock signal and the carry off clock signal, and generating a multi-sense enable signal having an on interval when at least one of the N carry clock signals has the on interval in response to the mode signal representing the multi-clock mode, and And a carry level shifter block adjusting voltage levels of the N carry clock signals to voltage levels suitable for a gate driver and supplying the N carry clock signals to the gate driver.
10. 10. The gate clock generator of claim 1, wherein the gate clock generator comprises a gate clock generator, The scan clock generator includes: A scan mode selection block determining an operation mode of the gate clock generator and generating a mode signal representing the determined operation mode; A scan pulse generator block generating the N scan clock signals based on the multi-sense enable signal, the scan on clock signal, and the scan off clock signal received from the carry clock generator in response to the mode signal representing the multi-clock mode, and generating the N scan clock signals based on the scan on clock signal and the scan off clock signal in response to the mode signal representing the operation mode different from the multi-clock mode, and And a scan level shifter block adjusting voltage levels of the N scan clock signals to voltage levels suitable for a gate driver and supplying the N scan clock signals to the gate driver.

Description

Gate clock generator and display device Technical Field The present invention relates to a display device, and more particularly, to a gate clock generator generating a gate clock signal for a gate driver and a display device including the same. Background The gate clock generator of the display device may receive a gate clock signal (e.g., a carry clock signal, a scan clock signal, and a sense clock signal) from a controller (e.g., a timing controller) of the display device, adjust a voltage level of the gate clock signal to a voltage level suitable for a gate driver of the display device, and provide the gate clock signal having the suitable voltage level to the gate driver. The gate driver may provide a scan signal and a sense signal to a plurality of pixels of the display device based on the gate clock signal. However, the gate clock generator of the related art has a problem in that the number of switches or the number of pulses of each gate clock signal is limited to a certain number (e.g., 4). Disclosure of Invention It is an object of the present invention to provide a gate clock generator supporting multiple clock modes. Another object of the present invention is to provide a display apparatus including a gate clock generator supporting a multi-clock mode. However, the technical problem to be solved by the present invention is not limited to the above-mentioned technical problem, and various extensions can be made without departing from the spirit and scope of the field of the present invention. In order to achieve an object of the present invention, a gate clock generator of a display device according to an embodiment of the present invention includes a carry clock generator sequentially generating N carry clock signals based on a carry on clock signal and a carry off clock signal, N being an integer of 2 or more, a scan clock generator generating N scan clock signals based on a scan on clock signal and a scan off clock signal, and a sense clock generator generating N sense clock signals based on a sense on clock signal and a sense off clock signal. In the multiple clock mode, during a conduction interval of a kth one of the N carry clock signals, the scan clock generator outputs, as a kth one of the N scan clock signals, the kth one of the pulses having a number corresponding to a number of pulses of the scan conduction clock signal in the conduction interval of the kth one of the carry clock signals, and the sense clock generator outputs, as a kth one of the N sense clock signals, the kth sense clock signal having a number of pulses corresponding to a number of pulses of the sense conduction clock signal in the conduction interval of the kth one of the carry clock signals, K being an integer of 1 or more and N or less. In an embodiment, the carry clock generator may provide the N carry clock signals to the scan clock generator and the sense clock generator in the multi-clock mode. In an embodiment, the scan clock generator may change the kth scan clock signal to an on level in response to each pulse of the scan on clock signal and change the kth scan clock signal to an off level in response to each pulse of the scan off clock signal during the on interval of the kth carry clock signal in the multi-clock mode, and the sense clock generator may change the kth sense clock signal to the on level in response to each pulse of the sense on clock signal and change the kth sense clock signal to the off level in response to each pulse of the sense off clock signal during the on interval of the kth carry clock signal. In one embodiment, the carry clock generator may include a carry mode selection block determining an operation mode of the gate clock generator and generating a mode signal representing the determined operation mode, a carry pulse generator block sequentially generating the N carry clock signals based on the carry on clock signal and the carry off clock signal and supplying the N carry clock signals to the scan clock generator and the sense clock generator in response to the mode signal representing the multi-clock mode, and a carry level shifter block adjusting voltage levels of the N carry clock signals to voltage levels suitable for a gate driver and supplying the N carry clock signals to the gate driver. In an embodiment, the scan clock generator may include a scan mode selection block determining an operation mode of the gate clock generator and generating a mode signal representing the determined operation mode, a scan pulse generator block generating the N scan clock signals based on the N carry clock signals, the scan on clock signals, and the scan off clock signals in response to the mode signal representing the multi-clock mode and generating the N scan clock signals based on the scan on clock signals and the scan off clock signals in response to the mode signal representing the operation mode different from the multi-clock mode, and a scan level shifter block adjusting voltage leve