CN-113948514-B - Semiconductor device and manufacturing method thereof

CN113948514BCN 113948514 BCN113948514 BCN 113948514BCN-113948514-B

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for reducing parasitic capacitance between adjacent storage contact parts and improving driving capability of the semiconductor device. The semiconductor device includes a substrate, a bit line structure, a memory contact, and an isolation portion. The substrate has an active region. A bit line structure is formed on the substrate and is in contact with a portion of the active region. The storage contact and the isolation are formed between two adjacent bit line structures. The storage contact is in contact with another portion of the active region. The isolation part is used for isolating two adjacent storage contact parts. The material contained in the spacer comprises a low-k material. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device provided by the technical scheme.

Inventors

GUO BINGRONG
YANG TAO
LU YIHONG
HU YANPENG

Assignees

中国科学院微电子研究所
真芯(北京)半导体有限责任公司

Dates

Publication Date: 20260505
Application Date: 20200717

Claims (10)

1. A semiconductor device, comprising: A substrate having an active region; a bit line structure formed on the substrate and contacting a portion of the active region; And the isolation part is used for isolating the adjacent two storage contact parts, the material contained in the isolation part comprises a low-k material, the k value of the low-k material is less than or equal to 2.8, and the low-k material is one or more of BN, siBN, siCN.
2. The semiconductor device according to claim 1, wherein a bottom of the isolation portion is higher than a bottom of the storage contact portion.
3. The semiconductor device of claim 1 or 2, wherein the bit line structure comprises a bit line body, a cap layer on the bit line body, and side walls on both sides of the bit line body and the cap layer.
4. A method of manufacturing a semiconductor device, comprising: providing a substrate with an active region; forming a bit line structure on the substrate in contact with a portion of the active region; And forming a storage contact part and an isolation part between two adjacent bit line structures, wherein the storage contact part is in contact with the other part of the corresponding active region, the isolation part is used for isolating the two adjacent storage contact parts, the material contained in the isolation part comprises a low-k material, the k value of the low-k material is less than or equal to 2.8, and the low-k material is one or more of BN, siBN, siCN.
5. The method of manufacturing a semiconductor device according to claim 4, wherein the forming a memory contact and a spacer between adjacent two of the bit line structures comprises: Forming a sacrificial layer between two adjacent bit line structures; processing the sacrificial layer in a preset area to form a first groove; forming the isolation part in the first groove; Removing the residual sacrificial layer, and etching the substrate downwards by taking the bit line structure and the isolation part as masks to form a second groove so as to expose another part of the active region between the adjacent bit line structures; the storage contact is formed in the second groove.
6. The method of manufacturing a semiconductor device according to claim 5, wherein the step of forming a sacrificial layer between two adjacent bit line structures comprises: Etching the substrate until the active region is exposed by taking the bit line structure as a mask to form a groove parallel to the bit line structure; and filling a sacrificial material in the groove to form a sacrificial layer.
7. The method for manufacturing a semiconductor device according to claim 5 or 6, wherein the material contained in the sacrificial layer includes SiO 2 and/or a carbon polymer.
8. The method for manufacturing a semiconductor device according to claim 5 or 6, wherein the forming the spacer in the first groove comprises: forming a low-k material on the substrate covering the bit line structure and the first recess; And performing node separation treatment on the low-k material to obtain the isolation part.
9. The method according to claim 8, wherein the node separation treatment is performed on the low-k material by plasma etching or wet etching.
10. The method according to claim 8, wherein when the node separation treatment is performed on the low-k material by wet etching, a solution used is an HF solution or a mixed solution containing HF, H 2 SO 4 、H 2 O 2 , and deionized water.

Description

Semiconductor device and manufacturing method thereof Technical Field The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background A contact structure is a structure that can interconnect an active region within a semiconductor device with a metal lead that is located outside of a dielectric layer. The electrical signal in the active region or the electrical signal in the metal lead can be transferred through the contact structure, thereby realizing corresponding operation of the semiconductor device. However, with the miniaturization of the semiconductor device, parasitic capacitance is generated between adjacent memory contacts, resulting in a decrease in driving capability of the semiconductor device, thereby making the operation performance of the semiconductor device poor. Disclosure of Invention The invention aims to provide a semiconductor device and a manufacturing method thereof, which are used for reducing parasitic capacitance between adjacent storage contact parts and improving driving capability of the semiconductor device. In order to achieve the above object, the present invention provides a semiconductor device including: A substrate having an active region; a bit line structure formed on the substrate and contacting a portion of the active region; And a storage contact portion formed between the adjacent two bit line structures, the storage contact portion being in contact with another portion of the active region, and an isolation portion for isolating the adjacent two storage contact portions, the isolation portion comprising a material comprising a low-k material. Compared with the prior art, in the semiconductor device provided by the invention, the storage contact part and the isolation part are formed between two adjacent bit line structures. The isolation part is used for isolating two adjacent storage contact parts. And, the spacer is formed of a low-k material. Specifically, the isolation portion formed of a low-k material has a low dielectric constant. Because the capacitance is in direct proportion to the dielectric constant, the dielectric constant of the isolation part between the adjacent storage contact parts is reduced, and the parasitic capacitance between the adjacent storage contact parts can be reduced, thereby improving the driving capability of the semiconductor device and the working performance of the semiconductor device. The invention also provides a manufacturing method of the semiconductor device, which comprises the following steps: providing a substrate with an active region; forming a bit line structure on the substrate in contact with a portion of the active region; and forming a storage contact portion and an isolation portion between two adjacent bit line structures, wherein the storage contact portion is in contact with another part of the active region, the isolation portion is used for isolating the two adjacent storage contact portions, and the material contained in the isolation portion comprises a low-k material. Compared with the prior art, the beneficial effects of the manufacturing method of the semiconductor device provided by the invention are the same as those of the semiconductor device provided by the technical scheme, and the description is omitted here. Drawings The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings, each drawing subscript a, b represents a cross-sectional view taken in the directions AA 'and BB' on top view, respectively. FIG. 1 is a top view of the bit line structure according to the embodiment of the present invention, wherein FIG. 1a is a top view along AA 'shown in FIG. 1, and FIG. 1b is a cross-sectional view along BB' shown in FIG. 1; Fig. 2 is a top view of a structure after forming a sacrificial layer according to an embodiment of the present invention, fig. 2a is a cross-sectional view along AA 'direction of the top view shown in fig. 2, and fig. 2b is a cross-sectional view along BB' direction of the top view shown in fig. 2; FIG. 3 is a top view of the structure after forming the first grooves according to the embodiment of the present invention, FIG. 3a is a cross-sectional view along AA 'of the top view shown in FIG. 3, and FIG. 3b is a cross-sectional view along BB' of the top view shown in FIG. 3; FIG. 4 is a top view of a structure after forming a low-k material according to an embodiment of the present invention, FIG. 4a is a cross-sectional view along direction AA 'of the top view shown in FIG. 4, and FIG. 4b is a cross-sectional view along direction BB' of the top view shown in FIG. 4; fig. 5 is a top view of a structu