CN-113948523-B - Memory forming method and three-dimensional memory

CN113948523BCN 113948523 BCN113948523 BCN 113948523BCN-113948523-B

Abstract

The application provides a memory forming method and a three-dimensional memory, the memory forming method comprises the steps of providing a substrate, wherein the substrate comprises a substrate and a laminated structure, the laminated structure is located on the exposed surface of the substrate, the laminated structure comprises sacrificial layers and insulating medium layers which are alternately arranged, a patterned mask layer is formed on the exposed surface of the laminated structure, the patterned mask layer comprises a slit area and an edge area which is located at one side of the slit area, the slit area comprises a plurality of channels penetrating to the surface of the laminated structure, the edge area comprises a first groove and/or a hole, the patterned mask layer is used as a mask, the laminated structure is etched to form a plurality of grid line slits, and the patterned mask layer is removed. The formation method of the memory better relieves the problems of etching stop, inclination and the like of the gate line slit at the edge, ensures that the etching effect of the gate line slit at the plane edge is better, and further ensures that the overall performance of the device is better.

Inventors

ZHAO XIANGHUI
ZENG ZUIXIN
SHAN JINGJING
DOU HAIQING
GAO YI

Assignees

长江存储科技有限责任公司
长江存储科技有限责任公司

Dates

Publication Date: 20260421
Application Date: 20211018
Priority Date: 20211018

Claims (9)

1. A method of forming a memory, comprising: Providing a substrate, wherein the substrate comprises a substrate and a laminated structure, the laminated structure is positioned on the exposed surface of the substrate, and the laminated structure comprises sacrificial layers and insulating medium layers which are alternately arranged; Forming a patterned mask layer on the exposed surface of the laminated structure, wherein the patterned mask layer comprises a slit area and an edge area at least positioned on one side of the slit area, the slit area comprises a plurality of channels penetrating to the surface of the laminated structure, and the edge area comprises a first groove and/or a hole; etching the laminated structure by taking the patterned mask layer as a mask to form a plurality of grid line slits; Removing the patterned mask layer; the number of the slit areas is multiple, the number of the edge areas is multiple, part of the edge areas are positioned between two adjacent slit areas, and the other edge areas are positioned at the edges of the slit areas.
2. The method of claim 1, wherein a critical dimension of the first recess is less than a critical dimension of the channel and a critical dimension of the hole is less than a critical dimension of the channel.
3. The method of claim 1 wherein the critical dimensions of each of the channels are the same.
4. The method of claim 1, wherein forming a patterned masking layer on an exposed surface of the laminate structure comprises: sequentially forming a mask material layer and a photoresist layer on the exposed surface of the laminated structure; removing part of the photoresist layer to form a plurality of first openings and at least one second opening penetrating to the surface of the mask material layer on the surface of the photoresist layer, wherein the rest of the photoresist layer is a photoresist part; Etching the mask material layer by taking the photoresist part as a mask to form the patterned mask layer, wherein the first opening corresponds to the channel, and the second opening corresponds to the first groove and/or the hole; and removing the photoresist portion.
5. The method of claim 4, wherein forming a masking material layer on an exposed surface of the laminate structure comprises: Forming a first sub-mask material layer on an exposed surface of the laminated structure; And forming a second sub-mask material layer on the exposed surface of the first sub-mask material layer.
6. The method of claim 5, wherein the material of the first sub-mask layer comprises carbon and the material of the second sub-mask layer comprises silicon oxynitride.
7. The method of claim 1, wherein after etching the stacked structure with the patterned mask layer as a mask to form a plurality of gate line slits, the method of forming the memory further comprises: And replacing all the sacrificial layers with a plurality of conductive layers to form a stacked structure, wherein the stacked structure comprises the conductive layers and the insulating medium layers which are alternately arranged.
8. The method of claim 7, wherein replacing all of the sacrificial layer with a plurality of conductive layers comprises: removing each sacrificial layer by adopting phosphoric acid to form a plurality of second grooves; And filling a conductive material in the second groove to form the conductive layer.
9. A three-dimensional memory fabricated by the method of forming a memory according to any one of claims 1 to 8, comprising: a base including a substrate and a laminated structure on an exposed surface of the substrate, the laminated structure including sacrificial layers and insulating dielectric layers alternately arranged; the grid line slits are positioned in the base, the grid line slits penetrate through the laminated structure to the surface of the substrate, the hole depths of the grid line slits are the same, the aperture of the grid line slits positioned in a first area is a first aperture, the aperture of the grid line slits positioned at the edge of a second area is a second aperture, the absolute value of the difference value between the first aperture and the second aperture is smaller than or equal to 1nm, the first area is the edge of the base, and the second area is the area of the base except the first area.

Description

Memory forming method and three-dimensional memory Technical Field The application relates to the field of semiconductors, in particular to a method for forming a memory and a three-dimensional memory. Background In the 3D NAND manufacturing process, as shown in fig. 1, each die (die) includes 4 plane areas (planes), and the gate line at PLANE EDGE (edges of the plane areas) has a serious loading effect (loading effect) during etching, which often causes abnormal stop and tilting (tilting) problems during etching of the gate line slit, resulting in poor effect of the obtained gate line slit, and further affects the device performance. The above information disclosed in the background section is only for enhancement of understanding of the background art from the technology described herein and, therefore, may contain some information that does not form the prior art that is already known in the country to a person of ordinary skill in the art. Disclosure of Invention The application provides a memory forming method and a three-dimensional memory, which are used for solving the problem of poor etching effect of a grid line slit at the edge of a plane. According to one aspect of the embodiment of the invention, a method for forming a memory is provided, wherein the substrate comprises a substrate and a laminated structure, the laminated structure is located on the exposed surface of the substrate and comprises sacrificial layers and insulating medium layers which are alternately arranged, a patterned mask layer is formed on the exposed surface of the laminated structure and comprises a slit area and an edge area located at one side of the slit area, the slit area comprises a plurality of channels penetrating to the surface of the laminated structure and comprises a first groove and/or a hole, the laminated structure is etched by taking the patterned mask layer as a mask to form a plurality of gate line slits, and the patterned mask layer is removed. Optionally, the critical dimension of the first groove is smaller than the critical dimension of the channel, and the critical dimension of the hole is smaller than the critical dimension of the channel. Optionally, the critical dimensions of each of the channels are the same. Optionally, there are a plurality of slit regions, the edge regions are a plurality of, a part of the edge regions are located between two adjacent slit regions, and the other edge regions are located at the edges of the slit regions. Optionally, forming a patterned mask layer on the exposed surface of the laminated structure, wherein the patterned mask layer comprises a mask material layer and a photoresist layer sequentially formed on the exposed surface of the laminated structure, removing part of the photoresist layer to form a plurality of first openings and at least one second opening penetrating to the surface of the mask material layer on the surface of the photoresist layer, and etching the mask material layer by taking the photoresist portion as a mask to form the patterned mask layer, wherein the first openings correspond to the channels, the second openings correspond to the first grooves and/or holes, and removing the photoresist portion. Optionally, forming a masking material layer on the exposed surface of the laminated structure includes forming a first sub-masking material layer on the exposed surface of the laminated structure and forming a second sub-masking material layer on the exposed surface of the first sub-masking material layer. Optionally, the material of the first sub-mask layer includes carbon, and the material of the second sub-mask layer includes silicon oxynitride. Optionally, after the patterning mask layer is used as a mask to etch the laminated structure to form a plurality of gate line slits, the method for forming the memory further comprises replacing all the sacrificial layers with a plurality of conductive layers to form a laminated structure, wherein the laminated structure comprises the conductive layers and the insulating medium layers which are alternately arranged. Optionally, replacing all the sacrificial layers with a plurality of conductive layers comprises removing each sacrificial layer with phosphoric acid to form a plurality of second grooves, and filling conductive materials in the second grooves to form the conductive layers. According to another aspect of the embodiment of the invention, a three-dimensional memory is provided, the three-dimensional memory comprises a substrate and a plurality of gate line slits, wherein the substrate comprises a substrate and a laminated structure, the laminated structure is positioned on the exposed surface of the substrate, the laminated structure comprises sacrificial layers and insulating medium layers which are alternately arranged, each gate line slit is positioned in the substrate, the gate line slits penetrate through the laminated structure to the surface of the substrate, the hole depths of the