CN-113972206-B - Semiconductor device, manufacturing method thereof and electronic equipment

CN113972206BCN 113972206 BCN113972206 BCN 113972206BCN-113972206-B

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment, which relate to the technical field of semiconductors and are used for solving the problems that a cap layer is etched when bit lines are etched, the occupied space of a side wall formed around the bit lines is enlarged, dispersion is poor and a side wall tailing structure is easy to form. The semiconductor device comprises a substrate, a cap layer, a bit line contact structure, a bit line forming control layer and a side wall forming control layer, wherein the substrate is provided with a unit area, a peripheral area and a partition area between the unit area and the peripheral area, the cap layer covers the unit area and the partition area, the bit line contact structure is arranged in the unit area and penetrates through the cap layer, the bit line is arranged in the unit area and is formed on the bit line contact structure, and the side wall forming control layer is formed between the bit line contact structure and the bit line. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device. The semiconductor device provided by the invention is used for electronic equipment.

Inventors

GUO BINGRONG
YANG TAO
LI JUNFENG
WANG WENWU

Assignees

中国科学院微电子研究所
真芯(北京)半导体有限责任公司

Dates

Publication Date: 20260505
Application Date: 20200723

Claims (10)

1. A semiconductor device, comprising: A substrate having a cell region, a peripheral region, and a partition region between the cell region and the peripheral region; a cap layer covering the cell region and the partition region; Bit line contact structures located in the cell regions, the bit line contact structures penetrating the cap layer; a bit line located in the cell region, the bit line being formed on the bit line contact structure; the side wall forming control layer is formed between the bit line contact structure and the bit line; The semiconductor device further comprises a gate stack arranged in the peripheral area, wherein the gate stack comprises a gate dielectric layer and a gate electrode, the gate dielectric layer is formed on the substrate, the gate electrode comprises an upper gate electrode and a lower gate electrode, the lower gate electrode is formed on the gate dielectric layer, the upper gate electrode stack is formed on the lower gate electrode, the side wall forming control layer and the upper gate electrode are formed by the same material, the side wall forming control layer, the upper gate electrode and the lower gate electrode are all made of conductive materials, and the conductive materials are doped polysilicon; the etching selection ratio of the bit line to the side wall forming control layer is larger than that of the bit line to the cap layer, and the material for manufacturing the bit line and the material for manufacturing the side wall forming control layer have similar metal characteristics.
2. The semiconductor device of claim 1, wherein the thickness of the sidewall forming control layer, the upper gate electrode and the lower gate electrode are all 10 nm-100 nm.
3. The semiconductor device according to claim 1 or 2, wherein the sidewall formation control layer is a single-layer sidewall formation control layer, or, The side wall forming control layer is a plurality of side wall forming control layers.
4. The semiconductor device of claim 1, wherein the cap layer is a silicon nitride cap layer, the cap layer further covering the peripheral region; a mask is formed between the substrate and the cap layer, and the mask is an oxide mask.
5. A method for manufacturing a semiconductor device, characterized in that the method for manufacturing a semiconductor device according to any one of claims 1 to 4 comprises: providing a substrate, wherein the substrate is provided with a unit area, a peripheral area and a partition area positioned between the unit area and the peripheral area; Forming a cap layer, a bit line contact structure and a side wall forming control layer on the substrate in sequence, wherein the cap layer covers the unit area and the partition area, and the bit line contact structure penetrates through the cap layer; Forming a side wall forming control layer on the bit line contact structure; and forming a bit line on the side wall forming control layer, wherein the bit line is positioned in the cell area.
6. The method of manufacturing a semiconductor device according to claim 5, wherein forming a cap layer, a bit line contact structure, and a sidewall formation control layer on the substrate comprises: forming a cap layer on the substrate; Forming the bit line contact structure on the cap layer; forming a lower gate electrode on the substrate at the peripheral region; Forming an upper gate electrode material layer on the cap layer and the lower gate electrode; And etching the upper gate electrode material layer to obtain a side wall forming control layer and an upper gate electrode positioned in the peripheral area, wherein the upper gate electrode covers the lower gate electrode.
7. The method of manufacturing a semiconductor device according to claim 6, wherein the forming a lower gate electrode in the peripheral region over the substrate comprises: Forming a lower gate electrode material layer on the cap layer and the gate dielectric layer; Etching the lower gate electrode material layer to obtain a lower gate electrode positioned on the gate dielectric layer; the thicknesses of the upper gate electrode material layer and the lower gate electrode material layer are 10 nm-100 nm.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the etching means in the etching of the lower gate electrode material layer comprises dry etching, or, Wet etching; wherein the dry etching includes plasma etching.
9. The method for manufacturing a semiconductor device according to claim 7, further comprising: The manufacturing method of the semiconductor device further comprises the step of forming a barrier layer on the cap layer before forming the lower gate electrode material layer on the cap layer and the gate dielectric layer, wherein the barrier layer covers the cell region, the peripheral region and the isolation region.
10. An electronic device comprising the semiconductor device according to any one of claims 1 to 4.

Description

Semiconductor device, manufacturing method thereof and electronic equipment Technical Field The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor device, a method for manufacturing the same, and an electronic apparatus. Background Dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM) represents whether a binary bit (bit) is a1 or 0 by using how much charge is stored in a capacitor. The DRAM has a simple structure, and each bit of data only needs one capacitor to be processed by one transistor. At the same time, DRAM density is high, and the capacity per unit volume is high, so that the cost is low. As the semiconductor memory device becomes highly integrated, in the process of manufacturing the DRAM, the cap layer is etched in the process of etching the bit line material layer to form the bit line, so that the space occupied by the sidewall formed around the bit line in the subsequent process becomes larger, and further, the space occupied by the sidewall is unevenly distributed in the wafer and the chip, and is scattered and deteriorated, and meanwhile, a sidewall tailing structure is easily formed, so that the performance of the semiconductor device is affected when the subsequent manufacturing process is performed. Disclosure of Invention The invention aims to provide a semiconductor device, a manufacturing method thereof and electronic equipment, which are used for avoiding the problems that the space occupied by a side wall formed around a bit line in the follow-up process is enlarged, the dispersion is poor and a side wall tailing structure is formed. In order to achieve the above object, the present invention provides a semiconductor device. The semiconductor device includes: a substrate having a cell region, a peripheral region, and a partition region between the cell region and the peripheral region; A cap layer covering the cell region and the partition region; Bit line contact structures located in the cell regions, the bit line contact structures penetrating the cap layer; Bit lines located in the cell regions, the bit lines being formed on the bit line contact structures; And forming a side wall forming control layer between the bit line contact structure and the bit line. Compared with the prior art, in the semiconductor device provided by the invention, the bit line contact structure penetrates through the cap layer, and the side wall forming control layer is formed between the bit line contact structure and the bit line. After the bit line material layer is formed on the surface of the side wall forming control layer, the cap layer is not directly etched when the bit line material layer is etched, on the one hand, the etched side wall forming control layer and the etched bit line are prevented from being controlled within a certain range, and meanwhile, funnel-shaped patterns are prevented from being formed below the bit line, so that the space size occupied by the side wall formed around the bit line is consistent with the design, the side wall forming control layer is distributed more uniformly in a wafer and a chip, the distribution is better, the formation of a side wall tailing structure is avoided, and the performance of a semiconductor device is improved. The invention also provides a manufacturing method of the semiconductor device. The manufacturing method of the semiconductor device comprises the following steps: Providing a substrate, wherein the substrate is provided with a unit area, a peripheral area and a partition area positioned between the unit area and the peripheral area; Sequentially forming a cap layer, a bit line contact structure and a side wall forming control layer on the substrate, wherein the cap layer covers the cell area and the partition area; forming a side wall forming control layer on the bit line contact structure; And forming bit lines on the side wall forming control layer, wherein the bit lines are positioned in the cell area. Compared with the prior art, the beneficial effects of the manufacturing method of the semiconductor device provided by the invention are the same as those of the semiconductor device described in the technical scheme, and the description is omitted here. The invention also provides electronic equipment comprising the semiconductor device of the technical scheme, and/or, The electronic equipment is communication equipment or terminal equipment. Compared with the prior art, the beneficial effects of the electronic equipment provided by the invention are the same as those of the semiconductor device described in the technical scheme, and the description is omitted here. Drawings The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and