CN-113972207-B - Semiconductor device, manufacturing method thereof and electronic equipment

CN113972207BCN 113972207 BCN113972207 BCN 113972207BCN-113972207-B

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment, which relate to the technical field of semiconductors and are used for solving the problem that a buffer layer is etched when bit lines are etched, so that the area of a storage node contact part formed subsequently is reduced, and a side wall tailing structure is formed. The semiconductor device includes a substrate having a cell region and a peripheral region, a buffer layer covering the cell region, a bit line contact structure located in the cell region, the bit line contact structure penetrating the buffer layer, a bit line formed on the bit line contact structure, and a conductive layer formed between the bit line contact structure and the bit line. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device. The semiconductor device provided by the invention is used for electronic equipment.

Inventors

GUO BINGRONG
YANG TAO
LI JUNFENG
WANG WENWU

Assignees

中国科学院微电子研究所
真芯(北京)半导体有限责任公司

Dates

Publication Date: 20260505
Application Date: 20200723

Claims (10)

1. A semiconductor device, comprising: A substrate having a cell region and a peripheral region; a buffer layer covering the cell region; Bit line contact structures located in the cell regions, the bit line contact structures penetrating the buffer layer; a bit line formed on the bit line contact structure; The etching selection ratio of the bit line to the conductive layer is larger than that of the bit line to the buffer layer; The buffer layer comprises at least one first buffer layer and at least one second buffer layer, wherein the at least one first buffer layer is formed on the substrate; The at least one first buffer layer comprises a mask and a buffer film, wherein the mask is formed on the substrate, and the buffer film is formed on the surface of the mask.
2. The semiconductor device according to claim 1, wherein the substrate further has a partition region between the cell region and the peripheral region, the buffer layer further covers the partition region, and/or, The semiconductor device further comprises a gate stack arranged in the peripheral area and the partition area, wherein the gate stack comprises a gate dielectric layer and a gate electrode, the gate dielectric layer is formed on the substrate, the gate dielectric layer is positioned in the peripheral area, the gate electrode is formed on the gate dielectric layer, the gate electrode is positioned in the peripheral area and the partition area, the gate electrode comprises an upper gate electrode and a lower gate electrode, the lower gate electrode is formed on the gate dielectric layer, and the upper gate electrode stack is formed on the lower gate electrode; the conductive layer and the upper gate electrode are formed of the same material, and/or, The materials contained in the conductive layer, the upper gate electrode and the lower gate electrode are all conductive materials, the conductive materials are doped polysilicon, and/or, The thicknesses of the conducting layer, the upper gate electrode and the lower gate electrode are all 10 nm-100 nm.
3. The semiconductor device according to claim 1 or 2, wherein the conductive layer is a single-layer conductive layer, or, The conductive layer is a multi-layer conductive layer.
4. The semiconductor device of claim 2, wherein the mask is an oxide mask, the buffer film is a silicon nitride buffer film, and the at least one second buffer layer comprises an oxide buffer film.
5. A method of manufacturing a semiconductor device, comprising: providing a substrate, wherein the substrate is provided with a unit area and a peripheral area; sequentially forming a buffer layer, a bit line contact structure and a conductive layer on the substrate, wherein the buffer layer covers the cell area; forming a conductive layer on the bit line contact structure; Forming bit lines on the conductive layers, wherein the etching selection ratio of the bit lines to the conductive layers is larger than that of the bit lines to the buffer layers; The buffer layer comprises at least one first buffer layer and at least one second buffer layer, wherein the at least one first buffer layer is formed on the substrate; The at least one first buffer layer comprises a mask and a buffer film, wherein the mask is formed on the substrate, and the buffer film is formed on the surface of the mask.
6. The method of manufacturing a semiconductor device according to claim 5, wherein the substrate further has a partition region between the cell region and the peripheral region, wherein forming a buffer layer, a bit line contact structure, and a conductive layer on the substrate comprises: forming a partition structure in the partition area: forming a buffer layer on the substrate, wherein the buffer layer also covers the isolation region; Forming a bit line contact structure on the buffer layer, and forming a lower gate electrode located in the peripheral region on the substrate; forming an upper gate electrode material layer on the buffer layer and the lower gate electrode; And processing the upper gate electrode material layer to obtain a conductive layer and an upper gate electrode positioned in the peripheral area, wherein the upper gate electrode covers the lower gate electrode.
7. The method of manufacturing a semiconductor device according to claim 6, wherein after forming a buffer layer over the substrate, a bit line contact structure is formed over the buffer layer, and before forming a lower gate electrode over the substrate in the peripheral region, the method further comprising: Patterning the buffer layer positioned in the peripheral area to expose an activation area of the peripheral area, and forming a gate dielectric layer on the activation area; Forming a bit line contact structure on the buffer layer, forming a lower gate electrode on the substrate in the peripheral region, comprising: forming a lower gate electrode material layer on the buffer layer and the gate dielectric layer; processing the lower gate electrode material layer and the buffer layer to obtain a bit line contact structure; Etching the lower gate electrode material layer to obtain a lower gate electrode positioned on the gate dielectric layer; the conductive layer and the upper gate electrode are formed of the same material, and/or, The materials contained in the conductive layer, the upper gate electrode material layer and the lower gate electrode material layer are conductive materials, the conductive materials are doped polysilicon, and/or, The thicknesses of the upper gate electrode material layer and the lower gate electrode material layer are 10 nm-100 nm.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the etching method used in patterning the buffer layer in the peripheral region comprises dry etching, or, Wet etching; wherein the dry etching includes plasma etching.
9. The method for manufacturing a semiconductor device according to claim 7, wherein after the forming of the lower gate electrode material layer on the buffer layer and the gate dielectric layer, the lower gate electrode material layer and the buffer layer are processed, and before the obtaining of the bit line contact structure, the method for manufacturing a semiconductor device further comprises: And forming a second mask on the lower gate electrode material layer, wherein the second mask is an oxide mask, and the second mask covers the cell region and the peripheral region.
10. An electronic device comprising the semiconductor device according to any one of claims 1 to 4, and/or, The electronic equipment is communication equipment or terminal equipment.

Description

Semiconductor device, manufacturing method thereof and electronic equipment Technical Field The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor device, a method for manufacturing the same, and an electronic apparatus. Background Dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM) represents whether a binary bit (bit) is a1 or 0 by using how much charge is stored in a capacitor. The DRAM has a simple structure, and each bit of data only needs one capacitor to be processed by one transistor. At the same time, DRAM density is high, and the capacity per unit volume is high, so that the cost is low. As semiconductor memory devices become highly integrated, the buffer layer is etched during the fabrication of DRAM, resulting in a reduced area of subsequently formed storage node contacts, and the easy formation of sidewall tailing structures, which affects the performance of the semiconductor device during subsequent fabrication processes. Disclosure of Invention The invention aims to provide a semiconductor device, a manufacturing method thereof and electronic equipment, which are used for avoiding the problem that a side wall tailing structure is formed by reducing the area of a storage node contact part formed later by etching a buffer layer when a bit line material layer is etched. In order to achieve the above object, the present invention provides a semiconductor device. The semiconductor device includes: A substrate having a cell region and a peripheral region; a buffer layer covering the cell region; Bit line contact structures located in the cell regions, the bit line contact structures penetrating the buffer layer; Bit lines formed on the bit line contact structures; and a conductive layer formed between the bit line contact structure and the bit line. Compared with the prior art, in the semiconductor device provided by the invention, the bit line contact structure penetrates through the buffer layer, the conductive layer is formed on the surface of the bit line contact structure, and the etching selectivity of the conductive layer is larger than that of the buffer layer. After the bit line material layer is formed on the surface of the conductive layer, the buffer layer is not directly etched on one hand, and on the other hand, the width of the etched conductive layer and bit line can be controlled within a certain range, funnel-shaped patterns can not be formed below the bit line, enough process allowance is reserved for forming a storage node contact part and forming a side wall subsequently, and a side wall tailing structure is avoided, so that the performance of the semiconductor device is improved. The invention also provides a manufacturing method of the semiconductor device. The manufacturing method of the semiconductor device comprises the following steps: providing a substrate, wherein the substrate is provided with a unit area and a peripheral area; Sequentially forming a buffer layer, a bit line contact structure and a conductive layer on a substrate, wherein the buffer layer covers a cell area; forming a conductive layer on the bit line contact structure; And forming a bit line on the conductive layer. Compared with the prior art, the beneficial effects of the manufacturing method of the semiconductor device provided by the invention are the same as those of the semiconductor device described in the technical scheme, and the description is omitted here. The invention also provides electronic equipment comprising the semiconductor device of the technical scheme, and/or, The electronic equipment is communication equipment or terminal equipment. Compared with the prior art, the beneficial effects of the electronic equipment provided by the invention are the same as those of the semiconductor device described in the technical scheme, and the description is omitted here. Drawings The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings: fig. 1 shows a layout of a semiconductor device provided by an embodiment of the present invention; fig. 2 shows a cross-sectional view of a prior art semiconductor device; fig. 3 shows a cross-sectional view of a semiconductor device provided by an embodiment of the present invention; fig. 4 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention; Fig. 5 to 14 are views showing cross-sectional embodiments along the line A-A' in fig. 1 at various stages in the manufacture of a semiconductor device in accordance with an embodiment of the present invention; FIG. 15 shows a schematic view of a cross-sectional embodiment along line A-A' in FIG. 1