CN-114023745-B - Semiconductor structure, preparation method thereof and three-dimensional memory

CN114023745BCN 114023745 BCN114023745 BCN 114023745BCN-114023745-B

Abstract

The invention discloses a semiconductor structure, a preparation method thereof and a three-dimensional memory, relates to the technical field of three-dimensional memory devices, and is used for providing a technical scheme of a step structure which can reduce photoetching times and has a better step side wall appearance. The preparation method of the semiconductor structure comprises the steps of providing a substrate, sequentially forming N stacked structures which are stacked on the substrate, sequentially carrying out m times of photoetching and etching on the N stacked structures to obtain a target step structure with N steps, wherein N is larger than m, and the N and the m meet a preset relation. A semiconductor structure, prepared according to the method for preparing the semiconductor structure. The three-dimensional memory comprises the semiconductor structure.

Inventors

GAO JIANFENG
LIU WEIBING
LI JUNJIE
ZHOU NA
XIANG JINJUAN
YANG TAO
LI JUNFENG
LUO JUN

Assignees

中国科学院微电子研究所

Dates

Publication Date: 20260508
Application Date: 20211029

Claims (8)

1. A method for preparing a semiconductor structure is characterized in that, the preparation method of the semiconductor structure comprises the following steps: Providing a substrate; Sequentially forming N stacking structures which are stacked on the substrate; sequentially carrying out m times of photoetching and etching on the N stacking structures to obtain a target step structure with N steps, wherein N is greater than m, and the N and m meet a preset relation; sequentially performing m times of photoetching and etching on the N stacking structures to obtain a target step structure with N steps, wherein the step structure comprises the following steps: Forming a first photoetching pattern on the N stacking structures, and removing the top insulating layers of preset areas of the N stacking structures by taking the first photoetching pattern as a mask to expose the sacrificial layers or the metal layers below the top insulating layers of the N stacking structures to obtain a first step structure, wherein the preset areas correspond to the areas where the target step structures are located; Forming a second photoetching pattern on the first step structure, and etching the first step structure by taking the second photoetching pattern as a mask in a bottom-up direction to obtain a second step structure; Forming a third photoetching pattern on the second step structure, and etching the second step structure by taking the third photoetching pattern as a mask in a bottom-up direction to obtain a third step structure, wherein the number of steps in the third step structure is 2 times that in the second step structure; forming a p+1st photoetching pattern on a p-th step structure, and etching the p-th step structure according to a bottom-up direction by taking the p+1st photoetching pattern as a mask to obtain the p+1st step structure, wherein the number of steps in the p+1st step structure is 2 times that in the p-th step structure; Forming an mth photoetching pattern on the mth step structure, and etching the mth step structure from bottom to top by taking the mth photoetching pattern as a mask to obtain the target step structure, wherein the number of steps in the target step structure is 2 times that in the mth step structure; The p+1-th photoetching pattern is formed on a target area of each step of the p-th step structure, wherein the p+1-th photoetching pattern is smaller than or equal to m-1, and the target area is a partial area where the step is connected with the last step.
2. The method of claim 1, wherein the predetermined relationship is: 。
3. The method of manufacturing a semiconductor structure according to claim 1, wherein each of the stacked structures includes a first sacrificial layer and a first insulating layer stacked from bottom to top; or, each of the stacked structures includes a first metal layer and a first insulating layer stacked from bottom to top.
4. A method of fabricating a semiconductor structure according to claim 3, wherein each step in the target step structure is formed at least by one or more photolithography and etching of the corresponding stacked structure.
5. A method of fabricating a semiconductor structure according to claim 3, wherein each of the steps comprises at least a second sacrificial layer formed by one or more of photolithography and etching of the first sacrificial layer in the respective stacked structure; or, each step at least comprises a second metal layer in the corresponding stacked structure, wherein the second metal layer is formed by one or more times of photoetching and etching of the first metal layer in the corresponding stacked structure.
6. The method of manufacturing a semiconductor structure according to claim 5, wherein when each of the steps includes at least the second sacrificial layer in the corresponding stacked structure, the method further comprises: removing the second sacrificial layer in the target step structure; and forming a third metal layer in the region where the second sacrificial layer is located, so as to obtain a new target step structure.
7. A semiconductor structure, characterized in that it is manufactured according to the method for manufacturing a semiconductor structure according to any one of claims 1-6.
8. A three-dimensional memory comprising the semiconductor structure of claim 7.

Description

Semiconductor structure, preparation method thereof and three-dimensional memory Technical Field The present invention relates to the field of three-dimensional memory devices, and in particular, to a semiconductor structure, a method for manufacturing the same, and a three-dimensional memory. Background Flash (Memory) Memory has evolved particularly rapidly in recent years. In order to further increase the Bit Density (Bit Density) of the flash memory while reducing the Bit Cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been rapidly developed. At the same time, there is a substantially identical integration requirement for other three-dimensional memory devices. In the existing three-dimensional structure, a step region needs to be formed at the periphery of the stacked structure so as to etch the contact hole later and connect the control electrode word line. In the step forming process, photoresist is used as a mask layer, and after the photoresist is transversely etched, the stacked structure is etched. Because the number of the step layers is large, in order to reduce the photoetching times and reduce the cost, a process of photoresist transverse Trim is mostly adopted, a plurality of steps can be formed under the condition of one photoetching, but the photoresist layer is transversely etched, and meanwhile, the photoresist layer is longitudinally etched, so that the photoresist layer is required to be consumed, and the thicker photoresist layer is required to be formed, otherwise, the problems of excessive photoresist layer consumption and damage to the step layers can occur. In addition, during lateral etching, a non-smooth side wall is easy to generate, which can lead to higher roughness of the side wall of the formed step when the photoresist mask pattern is transferred downwards to the lower layer film, thereby affecting the accuracy of the step size and the like. Disclosure of Invention The invention aims to provide a semiconductor structure, a preparation method thereof and a three-dimensional memory, which are used for providing a technical scheme of a step structure with reduced photoetching times and better step side wall morphology. The invention provides a preparation method of a semiconductor structure, which comprises the steps of providing a substrate, sequentially forming N stacked structures which are stacked on the substrate, sequentially carrying out m times of photoetching and etching on the N stacked structures to obtain a target step structure with N steps, wherein N is larger than m, and the N and the m meet a preset relation. Compared with the prior art, the preparation method of the semiconductor structure provided by the invention sequentially performs m times of photoetching and etching on N stacked structures to obtain the target step structure with N steps. Therefore, compared with the prior art, the method for forming each step in the target step structure by adopting the direct photoetching and etching method has the advantages that the uneven side wall is easy to generate by adopting the photoresist transverse Trim process, so that the roughness of the side wall of the formed step is higher when the photoresist mask pattern is transferred downwards to the lower layer film, and the accuracy of the step size is further affected. Furthermore, the number of steps in the target step structure is larger than the number of times of photoetching, so that the number of times of photoetching can be reduced. Preferably, the preset relationship is: N=2m-1。 Preferably, each of the stacked structures includes a first sacrificial layer and a first insulating layer stacked from bottom to top; or, each of the stacked structures includes a first metal layer and a first insulating layer stacked from bottom to top. Preferably, each step in the target step structure is formed by one or more photolithography and etching processes of the corresponding stacked structure. Preferably, each step includes at least a second sacrificial layer, and the second sacrificial layer is formed by one or more times of photoetching and etching of the first sacrificial layer in the corresponding stacked structure; or, each step at least comprises a second metal layer in the corresponding stacked structure, wherein the second metal layer is formed by one or more times of photoetching and etching of the first metal layer in the corresponding stacked structure. Preferably, when each step includes at least a second sacrificial layer in the corresponding stacked structure, the method for manufacturing a semiconductor structure further includes: removing the second sacrificial layer in the target step structure; and forming a third metal layer in the region where the second sacrificial layer is located, so as to obtain a new target step structure. Preferably, the sequentially performing the photolithography etching on the N stacked structures for m times, to obtain a target step structure wi