CN-114068392-B - Semiconductor structure and forming method thereof

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the substrate comprises a substrate, a grid structure arranged on the substrate, source-drain doped layers arranged on two sides of the grid structure and an interlayer dielectric layer arranged on the side part of the grid structure and covering the source-drain doped layers, a dielectric layer is formed on the grid structure and the interlayer dielectric layer, a first opening exposing the source-drain doped layers is formed by etching the dielectric layer and the interlayer dielectric layer, a first plug is formed in the first opening, a pattern definition layer is formed on the dielectric layer, a first groove corresponding to the grid structure is formed in the pattern definition layer, the dielectric layer exposed by etching the first groove is etched, a second opening exposing the grid structure is formed in the dielectric layer, the dielectric layer is easier to be etched than the first plug, the substrate at the bottom of the source-drain doped layer is not easy to be damaged in the second opening, the second plug formed in the second opening is not easy to be connected with the substrate, and the performance of the semiconductor structure can be improved.

Inventors

• ZHAO BINGGUI

Assignees

• 中芯国际集成电路制造(上海)有限公司
• 中芯国际集成电路制造(上海)有限公司
• 中芯国际集成电路制造(北京)有限公司
• 中芯国际集成电路制造(北京)有限公司

Dates

Publication Date

20260421

Application Date

20200731

Priority Date

20200731

Claims (19)

1. 1. A method of forming a semiconductor structure, comprising: Providing a substrate, wherein the substrate comprises a substrate, a gate structure positioned on the substrate, source and drain doping layers positioned on two sides of the gate structure, and an interlayer dielectric layer positioned on the side part of the gate structure and covering the source and drain doping layers; Forming a dielectric layer on the gate structure and the interlayer dielectric layer; etching the dielectric layer and the interlayer dielectric layer to form a first opening exposing the source-drain doped layer; forming a first plug in the first opening; forming a pattern definition layer on the dielectric layer after forming the first opening, wherein the pattern definition layer is provided with a first groove corresponding to the grid structure; Etching the dielectric layer exposed by the first groove after forming the first plug, and forming a second opening exposing the gate structure in the dielectric layer; Forming a second plug in the second opening; The step of etching the dielectric layer and forming a first opening exposing the source-drain doping layer in the dielectric layer comprises the steps of forming a pattern layer on the dielectric layer, patterning the pattern layer and forming a second groove in the pattern layer; after forming the first opening, patterning the pattern layer to form the pattern definition layer; forming the first plug in the first opening includes forming a first conductive material layer over the first recess, the second recess, the first opening, and the pattern defining layer; removing the first conductive material layer above the pattern definition layer; and removing the first conductive material layer in the first groove and the second groove, and taking the rest of the first conductive material layer in the first opening as the first plug.
2. 2. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the first recess, the first recess exposes a portion of the first opening.
3. 3. The method of forming a semiconductor structure of claim 1, wherein the material of the pattern definition layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbonitride, and boron carbon silicon nitride.
4. 4. The method of forming a semiconductor structure of claim 1, wherein the pattern defining layer has a thickness of 40 nm to 50 nm.
5. 5. The method of forming a semiconductor structure of claim 1, wherein the patterned layer is formed using a chemical vapor deposition process.
6. 6. The method of forming a semiconductor structure of claim 1, wherein the step of forming the pattern definition layer comprises: Forming an anti-reflection material layer in the first opening and on the pattern layer; forming a photoresist layer on the anti-reflection material layer; Etching the anti-reflection material layer by taking the photoresist layer as a mask to form an anti-reflection coating; And etching the pattern layer by taking the photoresist layer and the anti-reflection coating as masks, forming the first groove in the pattern layer, and taking the rest pattern layer as the pattern definition layer.
7. 7. The method of claim 1, wherein the dielectric layer and the interlayer dielectric layer exposed by the second recess are etched by a dry etching process to form a first opening exposing the source-drain doped layer.
8. 8. The method of forming a semiconductor structure of claim 1, wherein the first conductive material layer in the second recess and the first recess is removed using a dry etching process.
9. 9. The method of claim 1, wherein the dielectric layer exposed by the first recess is etched using a dry etching process, and a second opening exposing a gate structure is formed in the dielectric layer.
10. 10. The method of forming a semiconductor structure of claim 1, wherein forming a second plug in said second opening comprises forming a second conductive material layer in said second opening and over said dielectric layer, removing said second conductive material layer above said dielectric layer, the remaining second conductive material layer in said second opening acting as a second plug.
11. 11. The method of forming a semiconductor structure of claim 1, further comprising removing said pattern defining layer after forming said second opening and before forming said second plug.
12. 12. The method of forming a semiconductor structure of claim 11, wherein the pattern definition layer is removed using a wet etching process.
13. 13. The method of forming a semiconductor structure of claim 1, further comprising forming a mask layer over the dielectric layer prior to etching the dielectric layer; patterning the mask layer to form a second groove in the mask layer; etching the dielectric layer exposed by the second groove in the step of forming the first opening to form the first opening; the method for forming the semiconductor structure further comprises the steps of removing the mask layer after forming the first opening; After removing the mask layer, forming a first plug in the first opening; after the first plug is formed, the pattern definition layer with the first groove is formed on the dielectric layer.
14. 14. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, a gate cap layer is formed on the gate structure; in the step of forming the second opening, the gate cap layer is also etched.
15. 15. A semiconductor structure, comprising: The substrate comprises a substrate, a grid structure positioned on the substrate, source-drain doped layers positioned on two sides of the grid structure and an interlayer dielectric layer positioned on the side part of the grid structure and covering the source-drain doped layers; A dielectric layer on the substrate; the first plug penetrates through the dielectric layer and the interlayer dielectric layer and is connected with the source-drain doped layer; the pattern definition layer is positioned on the dielectric layer and provided with a first groove corresponding to the grid structure; and a second plug penetrating the dielectric layer and contacting the gate structure, wherein the second plug is formed after the pattern definition layer is removed, and the second plug is electrically isolated from the first plug based on the dielectric layer.
16. 16. The semiconductor structure of claim 15, wherein the material of the pattern defining layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbonitride, and boron carbon silicon nitride.
17. 17. The semiconductor structure of claim 15, wherein the pattern defining layer has a thickness of 40 nm to 50 nm.
18. 18. The semiconductor structure of claim 15, wherein the first recess exposes a portion of the first plug.
19. 19. The semiconductor structure of claim 15, wherein a gate cap layer is formed between the gate structure and the dielectric layer.

Description

Semiconductor structure and forming method thereof Technical Field Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same. Background In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called short channel effect (SCE: short-CHANNEL EFFECTS), is more likely to occur. Accordingly, to reduce the impact of short channel effects, semiconductor processes are gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, compared with a planar MOSFET, the gate structure has stronger control capability on a channel, can well inhibit short channel effect, and has better compatibility with the existing integrated circuit manufacturing compared with other devices. Disclosure of Invention The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the electrical performance of a device. In order to solve the problems, the embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate, a grid structure on the substrate, source and drain doped layers on two sides of the grid structure, an interlayer dielectric layer on the side of the grid structure and covering the source and drain doped layers, forming a dielectric layer on the grid structure and the interlayer dielectric layer, etching the dielectric layer and the interlayer dielectric layer to form a first opening exposing the source and drain doped layers, forming a first plug in the first opening, forming a pattern definition layer on the dielectric layer after the first opening is formed, forming a first groove corresponding to the grid structure in the pattern definition layer, etching the dielectric layer exposed by the first groove after the first plug is formed, forming a second opening exposing the grid structure in the dielectric layer, and forming a second plug in the second opening. Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises a substrate, a grid structure, a source-drain doped layer, an interlayer dielectric layer, a first plug and a pattern definition layer, wherein the grid structure is arranged on the substrate, the source-drain doped layer is arranged on two sides of the grid structure, the interlayer dielectric layer is arranged on the side part of the grid structure and covers the source-drain doped layer, the first plug penetrates through the dielectric layer and the interlayer dielectric layer and is connected with the source-drain doped layer, the pattern definition layer is arranged on the dielectric layer, and the pattern definition layer is provided with a first groove corresponding to the grid structure. Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages: In the method for forming a semiconductor structure provided by the embodiment of the invention, the first opening exposing the source-drain doped layer is formed in the dielectric layer, the first plug is formed in the first opening and is connected with the source-drain doped layer, the pattern definition layer is formed on the dielectric layer and is provided with the first groove corresponding to the grid structure, the dielectric layer exposed by the first groove is etched, the second opening exposing the grid structure is formed in the dielectric layer, in the step of forming the second opening, the etching difficulty of the dielectric layer is generally smaller than that of the first plug, so that the first plug is not easy to be damaged, the second opening is not easy to expose the substrate at the bottom of the source-drain doped layer, and the second plug formed in the second opening is not easy to be connected with the substrate, thereby being beneficial to improving the electrical performance of the semiconductor structure. Drawings Fig. 1 to 4 are schematic structural views corresponding to steps in a method for forming a semiconductor st