CN-114068484-B - Semiconductor package including stacked semiconductor chips

Abstract

The present application relates to a semiconductor package including stacked semiconductor chips. A semiconductor package includes a substrate and a sub-semiconductor package disposed on the substrate. The sub-semiconductor package includes a sub-semiconductor chip having a chip pad on an active surface thereof facing a substrate, a sub-molding layer surrounding a side surface of the sub-semiconductor chip and having one surface facing the substrate, and a redistribution conductive layer connected to the chip pad and extending on the one surface of the sub-molding layer. The redistribution conductive layer includes a signal redistribution conductive layer extending onto an edge of the sub-mold layer and having a signal redistribution pad at an end thereof, and a power redistribution conductive layer having a length shorter than a length of the signal redistribution conductive layer and having a power redistribution pad at an end thereof.

Inventors

• YAN ZHURI
• Pei Hanjun
• LI CHENGYE

Assignees

• 爱思开海力士有限公司
• 爱思开海力士有限公司

Dates

Publication Date

20260421

Application Date

20210322

Priority Date

20200731

Claims (20)

1. 1. A semiconductor package, the semiconductor package comprising: a substrate; A sub-semiconductor package disposed on the substrate and including: a sub-semiconductor chip having a chip pad on an effective surface thereof facing the substrate; a sub-mold layer surrounding a side surface of the sub-semiconductor chip and having one surface facing the substrate, and A redistribution conductive layer connected to the chip pad and extending over the one surface of the sub-mold layer, wherein the redistribution conductive layer comprises: A signal redistribution conductive layer extending onto an edge of the sub-mold layer and having a signal redistribution pad at an end of the signal redistribution conductive layer, and A power redistribution conductive layer having a length shorter than that of the signal redistribution conductive layer and having a power redistribution pad at an end of the power redistribution conductive layer; a signal sub-interconnect having an upper surface connected to the signal redistribution pad and a lower surface connected to the substrate; a power sub-interconnect having an upper surface connected to the power redistribution pad and a lower surface connected to the substrate; a capacitor formed in the sub-mold layer and electrically connected to the sub-semiconductor chip through the power redistribution conductive layer, and comprising: a first electrode having a lower surface connected to the power redistribution conductive layer; A second electrode having a lower surface connected to the power redistribution conductive layer, and A main body portion between the first electrode and the second electrode, and At least one main semiconductor chip formed on the sub-semiconductor package and electrically connected to the substrate, Wherein the capacitor is adjacent to the sub-semiconductor chip as compared to the power redistribution pad.
2. 2. The semiconductor package of claim 1, wherein, The power redistribution conductive layer includes: a first power redistribution conductive layer to which a ground voltage is applied, and A second power redistribution conductive layer to which a power supply voltage is applied, The first electrode is connected to the first power redistribution conductive layer, and The second electrode is connected to the second power redistribution conductive layer.
3. 3. The semiconductor package of claim 1, wherein each of the first and second electrodes is positioned between the power redistribution pad and the side surface of the sub-semiconductor chip.
4. 4. The semiconductor package of claim 2, wherein, At least one signal redistribution conductive layer is disposed between the first and second power redistribution conductive layers, and The body portion overlaps the at least one signal redistribution conductive layer.
5. 5. The semiconductor package of claim 2, wherein an alternating current, AC, path passes through the first power redistribution conductive layer, the capacitor, and the second power redistribution conductive layer.
6. 6. The semiconductor package of claim 1, wherein a power supply path through the power redistribution conductive layer, the power sub-interconnect, and the substrate is shorter than a signal transmission path through the signal redistribution conductive layer, the signal sub-interconnect, and the substrate.
7. 7. The semiconductor package of claim 1, wherein each of the signal sub-interconnect and the power sub-interconnect comprises at least one of a solder ball and a metal bump.
8. 8. The semiconductor package of claim 1, further comprising a main interconnect connecting the main semiconductor chip to the substrate, wherein, The signal sub-interconnector comprises an internal signal sub-interconnector for exchanging signals between the main semiconductor chip and the sub-semiconductor chip, The main interconnector comprises a signal main interconnector for exchanging the signals between the main semiconductor chip and the sub-semiconductor chips, The substrate includes an internal signal sub-substrate pad connected to the internal signal sub-interconnect and a signal main substrate pad connected to the signal main interconnect, and The internal signal sub-substrate pads and the signal main substrate pads are connected to each other by connection lines formed in the substrate.
9. 9. The semiconductor package of claim 1, further comprising a primary interconnect connecting the primary semiconductor chip to the substrate, wherein the primary interconnect comprises a bond wire.
10. 10. The semiconductor package of claim 1, wherein, The chip pads are disposed along first and second side edges of the sub-semiconductor chip in a first direction and along first and second side edges of the sub-semiconductor chip in a second direction, the second direction being perpendicular to the first direction, The signal redistribution pad includes a plurality of signal redistribution pads disposed at first and second side edges of the sub-mold layer in the first direction, The signal redistribution conductive layer comprises a plurality of signal redistribution conductive layers, The signal redistribution conductive layer connected to the chip pad disposed at the first side edge of the sub-semiconductor chip in the first direction and the first side edge of the sub-semiconductor chip in the second direction extends toward the signal redistribution pad disposed at the first side edge of the sub-mold layer in the first direction, and The signal redistribution conductive layer connected to the chip pads disposed at the second side edge of the sub-semiconductor chip in the first direction and at the second side edge of the sub-semiconductor chip in the second direction extends toward the signal redistribution pads disposed at the second side edge of the sub-mold layer in the first direction.
11. 11. The semiconductor package of claim 10, wherein the signal redistribution conductive layer has a spiral shape centered on the sub-semiconductor chip.
12. 12. The semiconductor package of claim 1, wherein, The substrate includes substrate pads disposed at first and second side edges of the substrate in a first direction, and The main semiconductor chip includes: At least one first main semiconductor chip connected to the substrate pad disposed at the first side edge of the substrate through a first main interconnect, and At least one second main semiconductor chip connected to the substrate pad disposed at the second side edge of the substrate through a second main interconnect.
13. 13. The semiconductor package of claim 12, wherein, The first main semiconductor chip includes a plurality of first main semiconductor chips stacked with an offset in a direction away from the first side edge of the substrate in the first direction, and The second main semiconductor chip includes a plurality of second main semiconductor chips stacked offset in a direction away from the second side edge of the substrate in the first direction.
14. 14. The semiconductor package of claim 1, wherein, The main semiconductor chip includes a memory, and The sub-semiconductor chip includes a memory controller.
15. 15. A semiconductor package, the semiconductor package comprising: a substrate; A sub-semiconductor package disposed on the substrate and including: a sub-semiconductor chip having a chip pad on an effective surface thereof facing the substrate; a sub-mold layer surrounding a side surface of the sub-semiconductor chip and having one surface facing the substrate, and A signal and power redistribution conductive layer connected to the die pad and extending to an edge of the sub-molding layer on the one surface of the sub-molding layer; a signal sub-interconnect having an upper surface connected to a signal redistribution pad formed at an end of the signal redistribution conductive layer and a lower surface connected to the substrate; a second power sub-interconnect having an upper surface connected to a second power redistribution pad formed at an end of the power redistribution conductive layer and a lower surface connected to the substrate; a first power sub-interconnect having an upper surface connected to a first power redistribution pad formed at a portion of the power redistribution conductive layer other than the end portion of the power redistribution conductive layer and a lower surface connected to the substrate; a capacitor formed in the sub-mold layer and electrically connected to the sub-semiconductor chip through the power redistribution conductive layer, and comprising: a first electrode having a lower surface connected to the power redistribution conductive layer; A second electrode having a lower surface connected to the power redistribution conductive layer, and A main body portion between the first electrode and the second electrode, and At least one main semiconductor chip formed on the sub-semiconductor package and electrically connected to the substrate, Wherein the capacitor is adjacent to the sub-semiconductor chip as compared to the first and second power redistribution pads.
16. 16. The semiconductor package of claim 15, wherein a power supply path through the power redistribution conductive layer, the first power sub-interconnect, and the substrate is shorter than a signal transmission path through the signal redistribution conductive layer, the signal sub-interconnect, and the substrate.
17. 17. The semiconductor package of claim 15, wherein, A first power supply path passing through the power redistribution conductive layer, the first power sub-interconnect, and the substrate, and A second power supply path passes through the power redistribution conductive layer, the second power sub-interconnect, and the substrate.
18. 18. The semiconductor package of claim 15, wherein each of the signal sub-interconnect, the first power sub-interconnect, and the second power sub-interconnect comprises at least one of a solder ball and a metal bump.
19. 19. The semiconductor package of claim 15, wherein, The chip pads are disposed along first and second side edges of the sub-semiconductor chip in a first direction and along first and second side edges of the sub-semiconductor chip in a second direction, the second direction being perpendicular to the first direction, The signal redistribution conductive layer comprises a plurality of signal redistribution conductive layers, signal redistribution pads are respectively formed at the end parts of the signal redistribution conductive layers, The power redistribution conductive layer comprises a plurality of power redistribution conductive layers, second power redistribution pads are respectively formed at the end parts of the power redistribution conductive layers, The signal redistribution pads and the second power redistribution pads are disposed at first and second side edges of the sub-mold layer in the first direction, The signal and power redistribution conductive layers connected to the chip pads disposed at the first side edge of the sub-semiconductor chip in the first direction and the first side edge of the sub-semiconductor chip in the second direction extend toward the signal and second power redistribution pads disposed at the first side edge of the sub-mold layer in the first direction, and The signal and power redistribution conductive layers connected to the chip pads disposed at the second side edge of the sub-semiconductor chip in the first direction and the second side edge of the sub-semiconductor chip in the second direction extend toward the signal and second power redistribution pads disposed at the second side edge of the sub-mold layer in the first direction.
20. 20. The semiconductor package of claim 19, wherein the signal redistribution conductive layer and the power redistribution conductive layer have a spiral shape centered on the sub-semiconductor chip.

Description

Semiconductor package including stacked semiconductor chips Technical Field The present patent document relates to a semiconductor package, and more particularly, to a semiconductor package in which a plurality of semiconductor chips are vertically stacked. Background As electronic products continue to shrink in size, the electronic products require capacity to handle large amounts of data. Accordingly, there is an increasing need to increase the integration of semiconductor devices used in these electronic products. However, it is difficult to perform a desired function with only a single semiconductor chip due to the limitation of semiconductor integration technology, and thus a semiconductor package having a plurality of semiconductor chips embedded therein is being manufactured. Disclosure of Invention In an embodiment, a semiconductor package includes a substrate and a sub-semiconductor package disposed on the substrate. The sub-semiconductor package includes a sub-semiconductor chip having a chip pad on an effective surface thereof facing the substrate, a sub-molding layer surrounding a side surface of the sub-semiconductor chip and having one surface facing the substrate, and a redistribution conductive layer connected to the chip pad and extending on the one surface of the sub-molding layer. The redistribution conductive layer includes a signal redistribution conductive layer extending onto an edge of the sub-mold layer and having a signal redistribution pad at an end thereof, and a power redistribution conductive layer having a length shorter than a length of the signal redistribution conductive layer and having a power redistribution pad at an end thereof. The semiconductor package further includes a signal sub-interconnect having an upper surface connected to the signal redistribution pad and a lower surface connected to the substrate, and a power sub-interconnect having an upper surface connected to the power redistribution pad and a lower surface connected to the substrate. The semiconductor package further includes a capacitor formed in the sub-mold layer. The capacitor includes a first electrode having a lower surface connected to the power redistribution conductive layer, a second electrode having a lower surface connected to the power redistribution conductive layer, and a body portion between the first electrode and the second electrode. The semiconductor package additionally includes at least one main semiconductor chip formed on the sub-semiconductor package and electrically connected to the substrate. In another embodiment, a semiconductor package includes a substrate and a sub-semiconductor package disposed on the substrate. The sub-semiconductor package includes a sub-semiconductor chip having a chip pad on an active surface thereof facing the substrate, a sub-molding layer surrounding a side surface of the sub-semiconductor chip and having one surface facing the substrate, and a signal redistribution conductive layer and a power redistribution conductive layer connected to the chip pad and extending to an edge of the sub-molding layer on the one surface of the sub-molding layer. The semiconductor package further includes a signal sub-interconnect having an upper surface connected to the signal redistribution pad formed at an end of the signal redistribution conductive layer and a lower surface connected to the substrate, a first power sub-interconnect having an upper surface connected to the first power redistribution pad formed at a portion of the power redistribution conductive layer other than the end of the power redistribution conductive layer and a lower surface connected to the substrate, and a capacitor formed in the sub-mold layer. The capacitor includes a first electrode having a lower surface connected to the power redistribution conductive layer, a second electrode having a lower surface connected to the power redistribution conductive layer, and a body portion between the first electrode and the second electrode. The semiconductor package further includes at least one main semiconductor chip formed on the sub-semiconductor package and electrically connected to the substrate. Drawings Fig. 1 is a plan view of a sub-semiconductor package according to an embodiment of the present disclosure, as seen from above. Fig. 2 is a cross-sectional view taken along line A1-A1' of fig. 1. Fig. 3 is a cross-sectional view taken along line A2-A2' of fig. 1. Fig. 4 is a cross-sectional view taken along line A3-A3' of fig. 1. Fig. 5 is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure, as seen from above. Fig. 6 is a plan view illustrating an upper surface of a substrate of the semiconductor package of fig. 5. Fig. 7 and 8 are cross-sectional views illustrating the semiconductor package of fig. 5. Fig. 9A is a diagram for describing an example of the effect of the semiconductor package according to the embodiment of the present disclosur