CN-114068536-B - Semiconductor device and manufacturing method thereof

CN114068536BCN 114068536 BCN114068536 BCN 114068536BCN-114068536-B

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, which relate to the technical field of semiconductor manufacturing and are used for solving the problem that the working performance of the semiconductor device is affected due to larger parasitic capacitance generated between a storage contact part and a bit line structure. The semiconductor device includes a semiconductor substrate having an active region, a bit line structure formed on the semiconductor substrate, the bit line structure including a contact portion, and a bit line body on the contact portion, the contact portion being in contact with one portion of the active region, and a storage contact portion formed between two adjacent bit line structures, the storage contact portion being in contact with another portion of the active region, wherein a portion of the bit line body above the contact portion has a lower top height than other portions of the bit line body. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device.

Inventors

GUO BINGRONG
YANG TAO
LU YIHONG
HU YANPENG

Assignees

中国科学院微电子研究所
真芯(北京)半导体有限责任公司

Dates

Publication Date: 20260505
Application Date: 20200730

Claims (9)

1. A semiconductor device, comprising: a semiconductor substrate having an active region; A bit line structure formed on the semiconductor substrate, the bit line structure including a contact portion, and a bit line body on the contact portion, the contact portion being in contact with a portion of the active region; And a storage contact formed between adjacent two of the bit line structures, the storage contact being in contact with another portion of the active region; Wherein a portion of the bit line body above the contact has a lower top height than other portions of the bit line body; The other parts of the bit line main body comprise a first transition part, a second transition part and a horizontal connection part, wherein the horizontal connection part is positioned between the first transition part and the second transition part, the top height of the horizontal connection part is larger than that of the bit line main body positioned on the contact part, and the horizontal connection part is connected with the bit line main body positioned on the contact part through the first transition part and the second transition part respectively.
2. The semiconductor device of claim 1, wherein a connection is included between the other portion of the bit line body and the semiconductor substrate, wherein a material of the connection includes polysilicon, and wherein a top surface of the connection is higher than a top surface of the contact.
3. The semiconductor device of claim 2, wherein the bit line structure further comprises an isolation layer on the bit line body; The semiconductor device further comprises side walls positioned on two sides of the connecting part, the contact part, the bit line main body and the isolation layer.
4. The semiconductor device of claim 1, wherein the bit line body comprises a barrier layer and a metal layer on the barrier layer, wherein a material of the barrier layer comprises one or more of TiN, taN, WN.
5. A method of manufacturing a semiconductor device, comprising: providing a semiconductor substrate with an active region; forming a semiconductor layer on the semiconductor substrate; Etching the semiconductor layer and the semiconductor substrate, and forming a contact hole on the semiconductor substrate, wherein the contact hole is contacted with one part of the active region; forming a contact material layer in the contact hole, wherein the top surface of the contact material layer is lower than the top surface of the semiconductor layer; Sequentially depositing a bit line material layer and an isolation material layer on the contact material layer and the semiconductor layer; Etching the isolation material layer, the bit line material layer, the contact material layer and the semiconductor layer to form an isolation layer, a bit line body, a contact portion and a connection portion; the bit line comprises a contact part, a bit line main body, a horizontal connecting part, a first transition part, a second transition part and a second transition part, wherein the other part of the bit line main body comprises the first transition part, the second transition part and the horizontal connecting part, the horizontal connecting part is positioned between the first transition part and the second transition part, the top height of the horizontal connecting part is larger than the top height of the bit line main body positioned on the contact part, and the horizontal connecting part is connected with the bit line main body positioned on the contact part through the first transition part and the second transition part respectively.
6. The method of manufacturing a semiconductor device according to claim 5, wherein side walls are formed on both sides of the isolation layer, the bit line body, the contact portion, and the connection portion.
7. The method for manufacturing a semiconductor device according to claim 6, wherein the method for manufacturing a semiconductor device further comprises: etching the semiconductor substrate by taking the isolation layer and the side wall as masks to form a groove; And forming storage contact parts in the grooves, and isolating structures between two adjacent storage contact parts.
8. The method of manufacturing a semiconductor device according to claim 5, wherein forming a contact material layer in the contact hole, a top surface of the contact material layer being lower than a top surface of the semiconductor layer, comprises: Depositing a doped polysilicon layer in the contact hole; and carrying out back etching on the doped polysilicon layer until the doped polysilicon layer is lower than the top surface of the semiconductor layer.
9. The method for manufacturing a semiconductor device according to claim 8, wherein the depth of the back etching is greater than 0nm and equal to or less than 50nm.

Description

Semiconductor device and manufacturing method thereof Technical Field The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background Fig. 1 shows a schematic diagram of a prior art semiconductor device structure. As shown in fig. 1, with the gradual miniaturization of the semiconductor device, parasitic capacitance is liable to occur between the memory contact portion 4 and the bit line structure 20. And parasitic capacitance c=ε·a/d, where ε is the relative permittivity, a is the area of the conductive portion (contact 200 and bit line body 201 above contact 200) in bit line structure 20 that is facing storage contact 4, and d is the vertical distance between bit line body 201 above contact 200 and storage contact 4. As is clear from the equation c=ε·a/d, the parasitic capacitance c is influenced by the facing area a between the conductive portion and the memory contact portion 4 in the bit line structure 20. As the integration level of semiconductor memory elements increases, parasitic capacitance generated between memory contact portions and bit line structures is large in the process of manufacturing DRAM, and driving capability of the semiconductor device is reduced in the process of operating the semiconductor device, thereby deteriorating the operating performance of the semiconductor device. Disclosure of Invention The invention provides a semiconductor device and a method for manufacturing the same, which are used for reducing parasitic capacitance generated between a storage contact part and a bit line structure. In order to achieve the above object, the present invention provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an active region; A bit line structure formed on the semiconductor substrate, the bit line structure including a contact portion, and a bit line body on the contact portion, the contact portion being in contact with a portion of the active region; and a storage contact formed between two adjacent bit line structures, the storage contact being in contact with another portion of the active region; wherein a portion of the bit line body above the contact has a lower top height than other portions of the bit line body. Compared with the prior art, in the semiconductor device provided by the invention, the bit line structure is formed on the semiconductor substrate, the bit line structure comprises the contact part and the bit line body positioned above the contact part, and the contact part is contacted with one part of the active region, so that the bit line body positioned above the contact part can be connected with one part of the active region through the contact part, and the other part of the bit line body is not connected with the active region. Meanwhile, a portion of the bit line body above the contact portion has a lower top height than other portions of the bit line body. At this time, along the length extending direction of the bit line body, the top height of the bit line body is changed in a curve or a broken line manner, and the top heights of all parts of the bit line body in the prior art are equal. In the semiconductor device provided by the invention, the part of the bit line main body above the contact part is provided with the top height lower than that of other parts of the bit line main body, so that the opposite areas between the contact part in the bit line structure and the bit line main body above the contact part and the storage contact part are smaller than the opposite areas between the contact part and the bit line main body above the contact part and the storage contact part in the prior art, thereby effectively reducing parasitic capacitance generated between the storage contact part and the bit line structure, and improving the driving capability of the semiconductor device and the working performance of the semiconductor device. The invention also provides a manufacturing method of the semiconductor device. The manufacturing method of the semiconductor device comprises the following steps: providing a semiconductor substrate with an active region; forming a semiconductor layer on a semiconductor substrate; Etching the semiconductor layer and the semiconductor substrate to form a contact hole on the semiconductor substrate, wherein the contact hole is contacted with one part of the active region; forming a contact material layer in the contact hole, wherein the top surface of the contact material layer is lower than the top surface of the semiconductor layer; sequentially depositing a bit line material layer and an isolation material layer on the contact material layer and the semiconductor layer; the isolation material layer, the bit line material layer, the contact material layer, and the semiconductor layer are etched to form an isolation layer, a bit line body, a contact portion,