CN-114068551-B - Source/drain integration in a three-node access device for a vertical three-dimensional (3D) memory

Abstract

The application relates to source/drain integration in a three-node access device of a vertical three-dimensional 3D memory. Example methods include methods for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of dielectric material and sacrificial material in repeated iterations to form a vertical stack. An etching process is used to form a first vertical opening exposing vertical sidewalls of the vertical stack adjacent to the first region of sacrificial material. The first region is selectively etched to form a first horizontal opening that removes the sacrificial material and is a first horizontal distance from the first vertical opening. A plurality of layers of first source/drain material, channel material, and second source/drain material are deposited in the first horizontal opening to form a three-node access device for memory cells among the array of vertically stacked memory cells.

Inventors

• S.E. Syris
• J. A. Smyth III
• LI SHIYU
• G.S. Sanghu
• A. SaidI vaheda

Assignees

• 美光科技公司

Dates

Publication Date

20260512

Application Date

20210629

Priority Date

20200806

Claims (20)

1. 1. A method for forming an array of vertically stacked memory cells, the array having horizontally oriented access devices and vertically oriented access lines, comprising: depositing alternating layers of dielectric material and sacrificial material in repeated iterations to form a vertical stack; forming a first vertical opening using a first etching process, thereby exposing vertical sidewalls of the vertical stack adjacent to a first portion of the sacrificial material; Selectively etching a first portion of the sacrificial material to form a first horizontal opening that removes the sacrificial material in a first region and is spaced apart from the first vertical opening by a first horizontal distance to form a first source/drain region and a second source/drain region that are horizontally separated by a channel region, and Multiple layers of first source/drain material, channel material, and second source/drain material are deposited in the first horizontal opening to form a three-node access device for memory cells among the array of vertically stacked memory cells.
2. 2. The method of claim 1, wherein depositing the multilayer first source/drain material comprises depositing a first material to form an electrical contact with a storage node at a distal end of the first horizontal opening relative to the first vertical opening.
3. 3. The method of any of claims 1-2, wherein depositing the multilayer first source/drain material comprises depositing a metal layer as a first material in the first horizontal opening that does not oxidize when in contact with an oxide semiconductor channel material.
4. 4. The method of any of claims 1-2, wherein depositing the multilayer first source/drain material comprises depositing a metal layer as a first material that forms a conductive oxide when in contact with an oxide channel material in the first horizontal opening.
5. 5. The method of claim 2, further comprising depositing a second material in electrical contact with the first material in the first horizontal opening using an atomic layer deposition ALD process, wherein the second material is a second semiconductor material having an electronic bandgap lower than an electronic bandgap of the channel material.
6. 6. A method for forming an array of vertically stacked memory cells, the array having horizontally oriented access devices and vertically oriented access lines, comprising: depositing alternating layers of dielectric material and sacrificial material in repeated iterations to form a vertical stack; Forming a plurality of first vertical openings having a first horizontal direction and a second horizontal direction through the vertical stack and extending primarily in the second horizontal direction to form an elongated vertical column with sidewalls in the vertical stack; conformally depositing a first conductive material over the gate dielectric material in the first vertical opening; removing portions of the first conductive material to form a plurality of individual vertical access lines along the sidewalls of the elongated vertical columns; forming a second vertical opening exposing a vertical sidewall of the vertical stack adjacent to the first portion of the sacrificial material; Selectively etching the first portion of the sacrificial material to form a first horizontal opening that removes the sacrificial material in a first region and is spaced a first horizontal distance from the first vertical opening, and A selective deposition process is used to deposit in the first horizontal opening: A plurality of layers of first source/drain material in electrical contact with a storage node at a distal end of the first horizontal opening relative to the first vertical opening; channel material, and A plurality of layers of second source/drain material for forming a three-node access device for memory cells among the array of vertically stacked memory cells.
7. 7. The method as recited in claim 6, further comprising: Depositing an Nth source/drain material of the multi-layer first source/drain material having an electronic bandgap intermediate to the electronic bandgap of the previous (N-1) th source/drain material and the electronic bandgap of the channel material, and An nth source/drain material of the multi-layer first source/drain material is deposited having a conduction band offset intermediate a conduction band offset of a previous (nth-1) source/drain material and a conduction band offset of the channel material.
8. 8. The method of claim 7, further comprising depositing the nth source/drain material of the plurality of layers of first source/drain material in coordination with depositing a previous (N-1) th source/drain material to form a compositionally graded contact material.
9. 9. The method of any of claims 6-7, further comprising depositing a channel material having a feedback channel passivation material and in electrical contact with an nth source/drain material.
10. 10. The method as recited in claim 9, further comprising: Depositing an indium-rich indium gallium zinc oxide IGZO channel material to form a first layer of the channel material in contact with a gate dielectric, and An indium-less material is deposited relative to the first layer to form a leakage suppression layer.
11. 11. A method for forming an array of vertically stacked memory cells, the array having horizontally oriented access devices and vertically oriented access lines, comprising: depositing alternating layers of dielectric material and sacrificial material in repeated iterations to form a vertical stack; Forming a plurality of first vertical openings having a first horizontal direction and a second horizontal direction through the vertical stack and extending primarily in the second horizontal direction to form an elongated vertical column with sidewalls in the vertical stack; conformally depositing a first conductive material over the gate dielectric material in the first vertical opening; removing portions of the first conductive material to form a plurality of individual vertical access lines along the sidewalls of the elongated vertical columns; forming a second vertical opening using a first etching process, thereby exposing vertical sidewalls of the vertical stack adjacent to the first portion of the sacrificial material; Selectively etching the first portion of the sacrificial material to form a first horizontal opening that removes the sacrificial material in a first region and is spaced a first horizontal distance from the first vertical opening, and Depositing in the first horizontal opening using an atomic layer deposition ALD process: A first source/drain material in electrical contact with a storage node at a distal end of the first horizontal opening relative to the first vertical opening; a channel material in electrical contact with the first source/drain material, and A plurality of layers of second source/drain material in electrical contact with the channel material to form a three-node access device for memory cells among the array of vertically stacked memory cells.
12. 12. The method of claim 11, wherein depositing the multilayer second source/drain material comprises depositing a first semiconductor material having: An electronic bandgap intermediate the electronic bandgap of the channel material and the electronic bandgap of a subsequent semiconductor material formed in electrical contact with the first semiconductor material, and A conduction band offset intermediate the conduction band offset of the channel material and a conduction band offset of a subsequent semiconductor material formed in electrical contact with the first semiconductor material.
13. 13. The method of claim 12, wherein depositing the multilayer second source/drain material comprises: depositing the first semiconductor material; depositing a second semiconductor material in electrical contact with the first semiconductor material, and The second semiconductor material selected based on having an electronic bandgap intermediate the electronic bandgap of the first semiconductor material and the electronic bandgap of the subsequent semiconductor material is deposited, the subsequent semiconductor material being formed in electrical contact with the second semiconductor material.
14. 14. The method of claim 12, wherein depositing the multilayer second source/drain material comprises: depositing the first semiconductor material; depositing a second semiconductor material in electrical contact with the first semiconductor material, and The second semiconductor material is deposited that is selected based on having a conduction band offset intermediate the conduction band offset of the first semiconductor material and a conduction band offset of a subsequent semiconductor material that is formed in electrical contact with the second semiconductor material.
15. 15. The method of any one of claims 11-12, further comprising integrating horizontally oriented digit lines to form electrical contacts with the multi-layer second source/drain material to form the three-node access device of the memory cell without body contact.
16. 16. The method of any one of claims 11-12, further comprising forming the vertically oriented access line to have a horizontal width (W) that is greater than a horizontal length (L) of the channel material and horizontally overlaps both the multilayer second source/drain material and the first source/drain material.
17. 17. The method of any one of claims 11-12, further comprising forming the vertically oriented access line to have a horizontal width (W) that is less than a horizontal length (L) of the channel material and that partially overlaps horizontally with both the multilayer second source/drain material and the first source/drain material.
18. 18. A memory device, comprising: an array of vertically stacked memory cells, the array of vertically stacked memory cells comprising: A horizontally oriented three-node access device having a multi-layer first source/drain region and a multi-layer second source/drain region separated by a channel region, and a gate opposite the channel region and separated therefrom by a gate dielectric, wherein the three-node access device does not have direct electrical contact with a body region of the three-node access device or the channel region, wherein the order of layers of the multi-layer first source/drain region is different from the order of layers of the multi-layer second source/drain region in a horizontal direction, and wherein the multi-layer first source/drain region has a first number of layers and the multi-layer second source/drain region has a second number of layers different from the first number of layers; A vertically oriented access line coupled to the gate and separated from the channel region by the gate dielectric; a horizontally oriented storage node electrically coupled to the multi-layered first source/drain region of the three-node access device, an A horizontally oriented digit line electrically coupled to the multi-layer second source/drain region of the three-node access device.
19. 19. The memory device of claim 18, wherein the three-node access device has three nodes including the multi-layer first source/drain region, the multi-layer second source/drain region, and the gate opposite the channel region, and is devoid of the direct electrical body contact.
20. 20. The memory device of any one of claims 18-19, wherein the channel region comprises a two-dimensional 2D material comprising one or more of a transition metal dichalcogenide.

Description

Source/drain integration in a three-node access device for a vertical three-dimensional (3D) memory Technical Field The present disclosure relates generally to memory devices, and more particularly to source/drain integration in a three-node access device of a vertical three-dimensional (3D) memory. Background The memory is typically implemented in electronic systems, such as computers, cellular telephones, hand-held devices, and the like. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and may include Random Access Memory (RAM), dynamic Random Access Memory (DRAM), static Random Access Memory (SRAM), and Synchronous Dynamic Random Access Memory (SDRAM). Nonvolatile memory can provide persistent data by retaining stored data when unpowered and can include NAND flash memory, NOR flash memory, nonvolatile Read Only Memory (NROM), phase change memory (e.g., phase change random access memory), resistive memory (e.g., resistive random access memory), cross point memory, ferroelectric random access memory (FeRAM), and the like. As design rules shrink, less semiconductor space may be fabricated for memories including DRAM arrays. Respective memory cells for a DRAM may include an access device, such as a transistor, having first and second source/drain regions separated by a channel region. The gate may be opposite the channel region and separated therefrom by a gate dielectric. An access line, such as a word line, is electrically connected to the gates of the DRAM cells. The DRAM cell may include a storage node, such as a capacitor cell, coupled to the digit line through an access device. The access device may be activated (e.g., in order to select a cell) by an access line coupled to the access transistor. The capacitor may store a charge (e.g., a logic "1" or "0") corresponding to the data value of the corresponding cell. Disclosure of Invention An aspect of the present disclosure relates to a method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines, the method comprising depositing alternating layers of dielectric material and sacrificial material in repeated iterations to form a vertical stack, forming a first vertical opening using a first etching process exposing vertical sidewalls of a first portion of the vertical stack adjacent the sacrificial material, selectively etching the first portion of the sacrificial material to form a first horizontal opening that removes the sacrificial material in a first region and is separated from the first vertical opening by a first horizontal distance to form first and second source/drain regions horizontally separated by a channel region, and depositing multiple layers of first, channel, and second source/drain materials in the first horizontal opening to form a three-node access device of a memory cell among the array of vertically stacked memory cells. Another aspect of the present disclosure relates to a method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines, the method comprising depositing alternating layers of dielectric material and sacrificial material in repeated iterations to form a vertical stack, forming a plurality of first vertical openings having a first horizontal direction and a second horizontal direction, through the vertical stack, and extending primarily in the second horizontal direction to form an elongated vertical column with sidewalls in the vertical stack, conformally depositing a first conductive material on gate dielectric material in the first vertical openings, removing portions of the first conductive material to form a plurality of separate vertical access lines along the sidewalls of the elongated vertical column, forming a second vertical opening exposing vertical sidewalls of a first portion of the sacrificial material in the vertical stack, selectively etching the first portion of the sacrificial material to form a first horizontal opening that removes the sacrificial material in a first region and is spaced apart from the first vertical opening, and forming a plurality of layers of memory cells in the vertical stack with respect to the first vertical openings, forming a second vertical access line in the vertical stack, and forming a plurality of layers of memory cells in contact with the first vertical stack with the first vertical openings at a distance from the first drain node. Another aspect of the present disclosure relates to a method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines, the method comprising depositing alternating layers of dielectric material and sacrificial material in repeated iterations to form a vertical stack, forming a plurality of first vertical openings