CN-114078498-B - Memory device, controller controlling the same, memory system including the same, and method of operating the same

Abstract

A method of operating a memory device includes receiving a training request for a data channel, detecting at least one mode parameter according to the training request, transmitting the detected mode parameter to an external device, setting at least one of an NRZ mode and a PAM4 mode as a transmission signaling mode based on mode register setting configuration information from the external device, and performing communication with the external device according to the set transmission signaling mode.

Inventors

• Zhao Juanrun
• ZHAO XIXI
• SUN YONGXUN
• Cui Rongtun
• Cui Zhenhuan

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20210817

Priority Date

20200821

Claims (17)

1. 1. A memory device, comprising: Memory device processing circuitry configured to: transmitting read data to a data channel according to a transmission signaling mode; Receiving write data from the data channel according to the transmission signaling mode; Storing the transmission signaling pattern, and Performing a training operation on the data channel in response to a training request received from an external device, to detect at least one mode parameter in the training operation, to select one of a first transmission signaling mode and a second transmission signaling mode as the transmission signaling mode using the detected mode parameter, and to output mode flag information associated with the detected mode parameter to the external device, Wherein the at least one mode parameter includes at least one of a termination voltage corresponding to the data channel, a current consumed by the memory device.
2. 2. The memory device of claim 1, wherein the first transmission signaling mode is a non-return-to-zero NRZ mode, and The second transmission signaling mode is a 4-level pulse amplitude modulation PAM4 mode.
3. 3. The memory device of claim 1, wherein the memory device processing circuitry comprises pattern detection circuitry comprising a termination voltage detector configured to detect the transmission signaling pattern by comparing the termination voltage to a reference voltage.
4. 4. The memory device of claim 1, wherein the memory device processing circuitry comprises pattern detection circuitry comprising a current detector configured to detect the transmission signaling pattern by comparing a current consumed by the memory device with a reference current.
5. 5. The memory device of claim 1, wherein the memory device processing circuit further comprises a transmitter, the transmitter comprising: A serializer configured to convert received parallel data into serial data according to the transmission signaling mode; a first driver configured to output converted serial data according to the first transmission signaling mode, and And a second driver configured to output the converted serial data according to the second transmission signaling mode.
6. 6. The memory device of claim 1, wherein the transmission signaling mode is an NRZ mode as a default mode, and And selecting the transmission signaling mode from the NRZ mode to be a PAM4 mode according to the at least one mode parameter.
7. 7. The memory device of claim 1, wherein the memory device processing circuitry comprises mode detection circuitry configured to send mode selection information associated with the selected transmission signaling mode to the external device.
8. 8. The memory device of claim 1, wherein the transmission signaling pattern is stored in the memory device processing circuit using a pattern register setting received from the external device.
9. 9. A method of operating a memory device, the method comprising: receiving a training request for a data channel; detecting at least one mode parameter according to the training request; Transmitting the detected mode parameter to an external device; Setting at least one of a non-return-to-zero NRZ mode and a 4-level pulse amplitude modulation (PAM 4) mode as a transmission signaling mode based on mode register setting configuration information from the external device, and Communication is performed with the external device according to the set transmission signaling mode, Wherein detecting the at least one mode parameter comprises: determining whether a current consumed by the memory device is higher than a reference current or It is determined whether a termination voltage corresponding to the data channel is higher than a reference voltage.
10. 10. The method of claim 9, further comprising: Communication is performed in the NRZ mode as a default mode.
11. 11. The method of claim 10, wherein setting the transmission signaling mode comprises selecting the PAM4 mode when the consumed current is higher than the reference current or when the termination voltage is higher than the reference voltage.
12. 12. The method of claim 9, further comprising: communication is performed in the PAM4 mode as a default mode, Wherein setting the transmission signaling mode includes selecting the NRZ mode when the consumed current is not higher than the reference current or when the termination voltage is not higher than the reference voltage.
13. 13. A memory system, comprising: A memory device configured to receive or transmit data over a data channel according to a transmission signaling mode selected from the first transmission signaling mode and the second transmission signaling mode, and A controller configured to control the memory device and to select the transmission signaling mode using at least one mode parameter, wherein the at least one mode parameter comprises at least one of a termination voltage corresponding to the data channel, a current consumed by the memory device, Wherein the memory device comprises: Memory device processing circuitry configured to: Storing the transmission signaling pattern, and A training request is received from the controller to detect at least one mode parameter associated with the data channel in response to the training request, and flag information associated with the detected at least one mode parameter is sent to the controller.
14. 14. The memory system of claim 13, wherein the controller comprises: a controller processing circuit corresponding to the data channel, and The controller processing circuitry is configured to make training requests for the data channel, and Wherein the transmission signaling pattern is detected by the memory device processing circuitry in accordance with the training request.
15. 15. The memory system of claim 13 wherein the controller is configured to communicate with the memory device according to a transmission signaling pattern stored in a pattern register.
16. 16. The memory system of claim 13, wherein one bit of data corresponding to each of a first voltage level and a second voltage level higher than the first voltage level is transmitted through the data channel according to the first transmission signaling mode.
17. 17. The memory system according to claim 13, wherein two bits of data corresponding to each of a first voltage level, a second voltage level higher than the first voltage level, a third voltage level higher than the second voltage level, and a fourth voltage level higher than the third voltage level are transmitted through the data channel according to the second transmission signaling mode.

Description

Memory device, controller controlling the same, memory system including the same, and method of operating the same Cross Reference to Related Applications The present application claims priority from korean patent application No.10-2020-0105217 filed in the korean intellectual property office on 21 st 8/2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field The present disclosure relates to a memory device, a controller controlling the memory device, a memory system including the memory device, and a method of operating the same. Background In general, the demand for higher speed and larger capacity data transmission continues to grow with the widespread deployment of mobile devices and the rapid increase in internet traffic. However, it may be difficult to use non-return-to-zero (NRZ) type coding based signal modulation schemes for meeting the increasing demand for higher speed and larger capacity data transmission. In recent years, pulse amplitude modulation (e.g., 4-level pulse amplitude modulation (PAM 4)) signaling schemes have been actively developed as alternatives to signal schemes for higher-speed and larger-capacity data transmission. Disclosure of Invention Example embodiments provide a memory device selecting a transmission signaling mode, a controller controlling the memory device, a memory system including the memory device, and a method of operating the same. According to an example embodiment, a memory device includes a memory device processing circuit configured to transmit read data to a data channel according to a transmission signaling mode, receive write data from the data channel according to the transmission signaling mode, store the transmission signaling mode, and perform a training operation on the data channel in response to a training request received from an external device to detect at least one mode parameter in the training operation, select one of a first transmission signaling mode and a second transmission signaling mode as the transmission signaling mode using the detected mode parameter, and output mode flag information associated with the detected mode parameter to the external device. According to an example embodiment, a method of operating a memory device includes receiving a training request for a data channel, detecting at least one mode parameter according to the training request, transmitting the detected mode parameter to an external device, setting at least one of a non-return-to-zero (NRZ) mode and a 4-level pulse amplitude modulation (PAM 4) mode as a transmission signaling mode based on mode register setting configuration information from the external device, and performing communication with the external device according to the set transmission signaling mode. According to an example embodiment, a memory system includes a memory device configured to receive or transmit data over a data channel according to a transmission signaling mode selected from a first transmission signaling mode and a second transmission signaling mode, and a controller configured to control the memory device and select the transmission signaling mode using at least one mode parameter. The memory device includes memory device processing circuitry configured to store the transmission signaling pattern, receive a training request from the controller, detect at least one pattern parameter associated with the data channel in response to the training request, and send flag information associated with the detected at least one pattern parameter to the controller. According to an example embodiment, a controller for controlling a memory device includes a controller processing circuit configured to generate a clock and output the clock to the memory device, generate a command address signal to operate the memory device, transmit the command address signal in response to the clock, and transmit and receive data to and from the memory device over a data channel according to a transmission signaling mode selected from a first transmission signaling mode and a second transmission signaling mode. The method includes receiving flag information associated with at least one mode parameter from the memory device during a training period of the memory device, and determining the transmission signaling mode as one of the first transmission signaling mode and the second transmission signaling mode using the flag information. Drawings The foregoing and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Fig. 1 is a diagram illustrating a memory system according to an example embodiment. Fig. 2A and 2B are diagrams illustrating transmission signaling according to example embodiments. Fig. 3 is a diagram illustrating a mode detection circuit according to an example embodiment. Fig. 4 is a diagram illustrating a termination volt