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CN-114078794-B - Semiconductor structure and manufacturing method thereof

CN114078794BCN 114078794 BCN114078794 BCN 114078794BCN-114078794-B

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof, the semiconductor structure includes a first wafer, a second wafer, a barrier layer, a via, and a conductive material. The first wafer has a conductive pad. The second wafer is arranged to overlap the first wafer and includes a through hole aligned with the conductive pad. The inner wall of the perforation is connected with the conductive pad. The barrier layer covers the inner wall of the through hole. The barrier layer includes a bottom. The bottom is covered with a conductive pad. A via extends from the bottom of the barrier layer into the conductive pad. The inner diameter of the connecting channel is smaller than the inner diameter of the perforation. The conductive material fills the through holes and the connecting channels and is connected to the conductive pads. In this way, the overall electrical properties can be further improved.

Inventors

  • SHI XINYI

Assignees

  • 南亚科技股份有限公司

Dates

Publication Date
20260505
Application Date
20200827
Priority Date
20200811

Claims (13)

  1. 1. A semiconductor structure, comprising: a first wafer having a conductive pad; A second wafer, which is overlapped with the first wafer and comprises a perforation aligned with the conductive pad, wherein the inner wall of the perforation is connected with the conductive pad; An insulating layer covering the inner wall of the perforation; A barrier layer covering the insulating layer, wherein the cross section of the barrier layer is of two opposite L-shaped structures, the barrier layer comprises a bottom, and the bottom directly covers the conductive pad; a via extending from the bottom of the barrier layer into the conductive pad, wherein the via has an inner diameter smaller than the inner diameter of the via and a top between the two L-shaped structures, and And the conductive material is filled in the through holes and the communication channels and is connected to the conductive pad, wherein the conductive material directly contacts the conductive pad, and the bottom surface of the conductive material is lower than the bottom surface of the bottom of the barrier layer.
  2. 2. The semiconductor structure of claim 1, wherein the conductive material extends into the conductive pad.
  3. 3. The semiconductor structure of claim 1, wherein the insulating layer interfaces with the conductive pad.
  4. 4. The semiconductor structure of claim 1, further comprising: an adhesion layer between the first and second wafers, the through-holes extending through the adhesion layer to interface with the conductive pads.
  5. 5. The semiconductor structure of claim 1, wherein the first wafer comprises a first substrate and a first dielectric layer on the first substrate, the conductive pad being on the first dielectric layer.
  6. 6. The semiconductor structure of claim 5, wherein the first substrate includes an active element therein, the active element being connected to the conductive pad by a trace located within the first dielectric layer.
  7. 7. The semiconductor structure of claim 5, wherein the second wafer comprises a second substrate and a second dielectric layer on the second substrate, the second wafer connecting the first dielectric layer and the conductive pad of the first wafer with the second dielectric layer.
  8. 8. The semiconductor structure of claim 7, wherein the second wafer further comprises a passivation layer on a surface of the second substrate opposite the second dielectric layer.
  9. 9.A method of fabricating a semiconductor structure, comprising: connecting the second wafer to the first wafer having the conductive pad; forming a through hole aligned with and connected to the conductive pad on the second wafer; forming an insulating layer covering the second wafer, the through holes and the conductive pads; Exposing the conductive pad through the bottom of the insulating layer; after exposing the conductive pad through the bottom of the insulating layer, depositing a barrier layer covering the insulating layer and the conductive pad in the through hole; forming a sacrificial material filled in the through hole and covering the second wafer; Forming a temporary via in the sacrificial material aligned with the conductive pad, the temporary via exposing the barrier layer; Etching the bottom of the barrier layer according to the temporary channel to form a connecting channel exposing the conductive pad, wherein the cross section of the barrier layer is of two opposite L-shaped structures, and the top of the connecting channel is positioned between the two L-shaped structures; removing the sacrificial material, and And filling conductive material into the through holes and the connecting channels, wherein the conductive material directly contacts the conductive pads, and the bottom surface of the conductive material is lower than the bottom surface of the bottom of the barrier layer.
  10. 10. The method of manufacturing a semiconductor structure of claim 9, further comprising: Providing a mask and a photoresist pattern on the sacrificial material, and Etching the temporary channel aligned to the conductive pad on the sacrificial material through the photomask and the photoresist pattern, wherein the temporary channel exposes the barrier layer.
  11. 11. The method of manufacturing a semiconductor structure of claim 9, further comprising: planarizing the conductive material.
  12. 12. The method of manufacturing a semiconductor structure of claim 9, further comprising: Thinning a second substrate of the second wafer, wherein a second dielectric layer is located on the second substrate.
  13. 13. The method of manufacturing a semiconductor structure of claim 12, further comprising: And forming a passivation layer on the second substrate, wherein the passivation layer is formed on the other surface opposite to the second dielectric layer.

Description

Semiconductor structure and manufacturing method thereof Technical Field The invention relates to a semiconductor structure and a manufacturing method thereof. Background In a semiconductor structure, electrical connection between devices is performed by forming vias. In order to avoid unintended electrical connection and to protect the via structure, the barrier layer should be filled with a sufficient thickness in the via. However, in the process, this corresponds to depositing a residual thick barrier layer material at the bottom of the via, affecting the connection of the conductive material within the via and thus the overall electrical properties. Therefore, how to improve the electrical problem caused by the accumulated thickness of the barrier layer at the bottom of the via is one of the problems to be solved by those skilled in the art. Disclosure of Invention An object of the present invention is to provide a semiconductor structure capable of further improving the overall electrical properties of the semiconductor structure. According to one embodiment of the present invention, a semiconductor structure includes a first wafer, a second wafer, a barrier layer, a via, and a conductive material. The first wafer has a conductive pad. The second wafer is arranged to overlap the first wafer and includes a through hole aligned with the conductive pad. The inner wall of the perforation is connected with the conductive pad. The barrier layer covers the inner wall of the through hole and comprises a bottom, and the bottom of the barrier layer covers the conductive pad. A via extends from the bottom of the barrier layer into the conductive pad. The inner diameter of the connecting channel is smaller than the inner diameter of the perforation. The conductive material fills the through holes and the connecting channels and is connected to the conductive pads. In one or more embodiments, the conductive material extends into the conductive pad. In one or more embodiments, the semiconductor structure further includes an insulating layer. The insulating layer is located between the inner wall of the through hole and the barrier layer and is connected with the conductive pad. In one or more embodiments, the semiconductor structure further includes an adhesion layer. The adhesive layer is located between the first wafer and the second wafer. The perforations extend through the adhesive layer to interface with the conductive pads. In one or more embodiments, a first wafer includes a first substrate and a first dielectric layer on the first substrate. The conductive pad is located on the first dielectric layer. In some embodiments, the first substrate includes an active element therein. The active device is connected to the conductive pad through a line in the first dielectric layer. In some embodiments, the second wafer includes a second substrate and a second dielectric layer on the second substrate. The second wafer is connected with the first dielectric layer and the conductive pad of the first wafer through the second dielectric layer. In some embodiments, the second wafer further comprises a passivation layer. The passivation layer is positioned on the surface of the second substrate opposite to the second dielectric layer. An object of the present invention is to provide a method for manufacturing a semiconductor structure. According to one embodiment of the present invention, a method for manufacturing a semiconductor structure includes the following steps. The second wafer is connected to the first wafer having the conductive pad. A through hole aligned with and connected to the conductive pad is formed on the second wafer. A barrier layer is deposited covering the vias and the conductive pads. A sacrificial material is formed that fills the through-holes and covers the second wafer. A temporary via is formed in the sacrificial material in alignment with the conductive pad, the temporary via exposing the barrier layer. Etching the bottom of the barrier layer according to the temporary channel to form a communication channel exposing the conductive pad. The sacrificial material is removed. Filling conductive material into the through holes and the communication channels. In one or more embodiments, the semiconductor structure manufacturing method further includes the following flow. Before depositing the barrier layer, an insulating layer is formed to cover the second wafer, the through holes and the conductive pads. The conductive pad is exposed through the bottom of the insulating layer, wherein the barrier layer further covers the insulating layer after the barrier layer is deposited. In one or more embodiments, the semiconductor structure manufacturing method further includes the following flow. A mask and a photoresist pattern are disposed over the sacrificial material. A temporary channel aligned to the conductive pad is etched in the sacrificial material through the mask and the photoresist pattern, th