Search

CN-114093784-B - Wafer packaging method, device, electronic equipment and storage medium

CN114093784BCN 114093784 BCN114093784 BCN 114093784BCN-114093784-B

Abstract

The application provides a wafer packaging method, a device, electronic equipment and a storage medium, and relates to the technical field of semiconductors, wherein the method comprises the steps of carrying out wafer testing on a wafer to obtain a test wafer diagram corresponding to the wafer, wherein the test wafer diagram records the position of each chip in the wafer and a corresponding test result; and superposing a plurality of test wafer maps based on the test result, determining whether the chip at each position in the wafers is a risk chip, generating a target wafer map, and packaging the wafers based on the target wafer map. The method provided by the embodiment of the application can improve the risk chip rejection efficiency.

Inventors

  • GU QIANG
  • DAI WENSONG

Assignees

  • 上海物骐微电子有限公司

Dates

Publication Date
20260505
Application Date
20211125

Claims (8)

  1. 1. A method of wafer packaging, comprising: carrying out wafer testing on a wafer to obtain a testing wafer diagram corresponding to the wafer, wherein the position of each chip in the wafer and a corresponding testing result are recorded in the testing wafer diagram; Superposing a plurality of the test wafer maps based on the test result, determining whether the chip at each position in the wafers is a risk chip, generating a target wafer map, and Packaging the plurality of wafers based on the target wafer map; The method comprises the steps of superposing a plurality of test wafer graphs based on the test result, namely taking a first test wafer graph as an initial wafer graph, sequentially reading the next test wafer graph and comparing the next test wafer graph with a reference wafer graph to obtain a comparison result, determining whether chips at each position in the test wafer graph are risk chips or not, reading failure information of each chip from the test wafer graph, wherein the failure information comprises failure states, failure items and chip positions of the chips; The method comprises the steps of sequentially reading a next test wafer map and comparing the next test wafer map with a reference wafer map to obtain a comparison result, and determining whether chips at each position in the test wafer map are risk chips or not, wherein the step of comparing the test wafer map with the reference wafer map bit by bit, the step of recording the failure position and determining the chips corresponding to the failure position as risk chips when the first position in the test wafer map is the failure position, the step of determining whether the positions, related to the first position, in the reference wafer map are failure positions when the first position in the test wafer map is the qualified position, and the step of determining the chips corresponding to the qualified position as risk chips if the first position is the failure position.
  2. 2. The method of claim 1, wherein prior to the wafer testing the wafer, the method further comprises: Sequentially reading the next test wafer map by taking the first test wafer map of the designated batch as an initial reference wafer map and comparing the next test wafer map with the initial reference wafer map to obtain a comparison result, and Updating the initial reference wafer map based on the comparison result, and obtaining the reference wafer map after a plurality of test wafer maps are read and updated based on the comparison result.
  3. 3. The method of claim 1, wherein the encapsulating the plurality of wafers based on the target wafer map comprises: Counting the times that chips corresponding to each position in the plurality of test wafer diagrams are the risk chips, and determining an abnormal area in the target wafer diagram; and removing the chips in the abnormal region in the wafer, and packaging other chips in the wafer.
  4. 4. The method of claim 1, wherein the encapsulating the plurality of wafers based on the target wafer map comprises: Acquiring failure items corresponding to chips at each position in the test wafer map; receiving a rejection instruction, wherein the rejection instruction comprises a failure item to be rejected; Marking the target position of the chip corresponding to the reject instruction in the target wafer map, and And removing chips related to the target position in the wafer based on a preset removing scheme, and packaging other chips in the wafer.
  5. 5. The method of claim 1, wherein the acquiring a test wafer map corresponding to the wafer comprises: importing test data of wafer test into JMP software, and And converting the test data into the test wafer map based on a graph generator in the JMP software.
  6. 6. A wafer packaging apparatus, comprising: the testing module is used for testing the wafer to obtain a testing wafer diagram corresponding to the wafer, wherein the position of each chip in the wafer and a corresponding testing result are recorded in the testing wafer diagram; A superposition module for superposing a plurality of the test wafer maps based on the test result, determining whether the chip at each position in the plurality of wafers is a risk chip, generating a target wafer map, and The packaging module is used for packaging the wafers based on the target wafer map; The superposition module is specifically configured to take a first test wafer map as an initial wafer map, sequentially read a next test wafer map and compare the next test wafer map with a reference wafer map to obtain a comparison result, determine whether a chip at each position in the test wafer map is the risk chip, read failure information of each chip from the test wafer map, where the failure information includes failure states, failure items and chip positions of the chips; The superposition module is further used for comparing the test wafer map with the reference wafer map bit by bit, recording the failure position and determining that the chip corresponding to the failure position is the risk chip when the first position in the test wafer map is the failure position, determining whether the position related to the first position in the reference wafer map is the failure position when the first position in the test wafer map is the qualified position, and determining that the chip corresponding to the qualified position is the risk chip if the position related to the first position in the reference wafer map is the failure position.
  7. 7. An electronic device comprising a memory and a processor, the memory having stored therein program instructions which, when executed by the processor, perform the steps of the method of any of claims 1-5.
  8. 8. A computer readable storage medium, characterized in that the computer readable storage medium has stored therein computer program instructions which, when executed by a processor, perform the steps of the method according to any of claims 1-5.

Description

Wafer packaging method, device, electronic equipment and storage medium Technical Field The present application relates to the field of semiconductors, and in particular, to a wafer packaging method, a device, an electronic apparatus, and a storage medium. Background At present, the chip integration level is higher and higher, the chip test is also more and more complex, and in the application fields with high requirements on the chip quality, such as automobile electronics, industrial-grade chips and the like, if an area is abnormal in the wafer manufacturing engineering, the same risk exists in the area nearby the area. However, during the testing process, the chips in these areas are often not screened out by the testing due to critical or non-fatal physical damage, so that the chips finally flow into the clients, resulting in great loss. At present, the failure rate of the chip is required to be reduced or the failure rate of the chip is required to be ensured to meet the requirement, and each chip is required to be detected, so that the efficiency of detecting and eliminating the risk chips is low. Disclosure of Invention The embodiment of the application aims to provide a wafer packaging method, a wafer packaging device, electronic equipment and a storage medium, which are used for improving the risk chip removing efficiency. In a first aspect, an embodiment of the present application provides a wafer packaging method, including: carrying out wafer testing on a wafer to obtain a testing wafer diagram corresponding to the wafer, wherein the position of each chip in the wafer and a corresponding testing result are recorded in the testing wafer diagram; Superposing a plurality of the test wafer maps based on the test result, determining whether the chip at each position in the wafers is a risk chip, generating a target wafer map, and And packaging the plurality of wafers based on the target wafer map. In the implementation process, the test wafer graphs of the plurality of wafers are overlapped to generate the target wafer graph which can more obviously embody the abnormal area of the wafers, so that the risk area where the risk chips in the same batch of wafers are located is determined, and the chips in the wafers are packaged through the target wafer graph, so that the problem of time cost increase caused by detection of each chip can be avoided, the risk chips which are possibly screened and leaked can be rapidly removed, and the quality of the chips is improved. Optionally, the superimposing a plurality of the test wafer maps based on the test result includes: taking the first test wafer diagram as an initial wafer diagram, sequentially reading the next test wafer diagram and comparing the next test wafer diagram with a reference wafer diagram to obtain a comparison result, determining whether chips at each position in the test wafer diagram are risk chips or not, and And updating the initial wafer map based on the comparison result, and obtaining the target wafer map after reading a plurality of test wafer maps and updating the initial wafer map based on the comparison result. In the implementation process, the risk area is determined in the target wafer map by superposing the failure information in the plurality of wafers, and when the wafers are packaged, a plurality of wafers in a batch can be packaged based on one target wafer map, so that the quality of chips can be improved, and the packaging efficiency is improved. Meanwhile, failure tracking can be performed on the risk chip based on the target wafer map, so that the reason for the abnormality of the area can be conveniently found out. Optionally, the sequentially reading the next test wafer map and comparing the next test wafer map with the reference wafer map to obtain a comparison result, and determining whether the chip at each position in the test wafer map is the risk chip includes: Comparing the test wafer map with the reference wafer map bit by bit; When a first position in the test wafer diagram is a failure position, recording the failure position and determining that a chip corresponding to the failure position is the risk chip; And when the first position in the test wafer map is a qualified position, determining whether the position related to the first position in the reference wafer map is a failure position, and if so, determining that the chip corresponding to the qualified position is the risk chip. In the implementation process, a mode of generating a reference wafer map is adopted, a test wafer map of a set batch is superimposed to generate the reference wafer map, the quality risk of chips at any positions in the wafer is determined through the reference wafer map, and then the reference wafer map and the test wafer map are compared to remove the chips at the corresponding positions, so that the yield of the chips can be improved, and the removal efficiency of the chips at risk is improved. Optionally, before the wafer