CN-114093810-B - Chip and design method thereof

CN114093810BCN 114093810 BCN114093810 BCN 114093810BCN-114093810-B

Abstract

The embodiment of the application provides a chip and a design method thereof, wherein the method comprises the steps of determining the power consumption of at least two different areas on the chip according to the distribution parameters of a plurality of standard units on the chip; and adjusting the distribution parameters of at least two through silicon vias on the chip according to the power consumption of the at least two different areas, and adjusting the distribution positions of a plurality of standard units on the chip according to the adjusted distribution parameters of the through silicon vias.

Inventors

YANG YI
WANG YIYUAN
XUE YINGFEI
WANG XILONG

Assignees

芯盟科技有限公司

Dates

Publication Date: 20260512
Application Date: 20211019

Claims (10)

1. A method of chip design, the method comprising: The method comprises the steps of realizing the layout and wiring of a chip based on the back silicon through hole layout of a fixed mode in the initial stage of chip design, simulating according to turnover rate data provided by front-end design, and determining the power consumption of at least two different areas on the chip; According to the power consumption of the at least two different areas, adjusting the distribution parameters of at least two through silicon vias on the chip; According to the adjusted distribution parameters of the through silicon vias, adjusting the distribution positions of a plurality of standard units on the chip comprises rearranging the standard units in the adjusted through silicon via coordinate range outside the coverage area of the through silicon vias.
2. The method of claim 1, wherein adjusting distribution parameters of at least two through silicon vias on the chip according to power consumption of the at least two different regions comprises: determining a first area on the chip where power consumption is greater than a first threshold; And adjusting the distribution parameters of the through silicon vias in the first region.
3. The method of claim 2, wherein the adjusting the distribution parameter of the through silicon vias in the first region comprises: increasing the cross-sectional area of the through silicon via in the first region, and/or And adding the through silicon vias in the first region.
4. The method of claim 3, wherein the increasing the cross-sectional area of the through silicon via in the first region comprises: And if the first region comprises at least one through silicon via, increasing the sectional area of at least one through silicon via in the first region.
5. The method of claim 3, wherein the adding the through silicon via within the first region comprises: and if the first region does not comprise the through silicon vias, adding at least one through silicon via in the first region.
6. The method of claim 5, wherein adding at least one of the through silicon vias in the first region if the through silicon vias are not included in the first region comprises: Determining a first through silicon via located outside the first region, and an abscissa located within an abscissa range of the first region; at least one second through silicon via is added in the first region.
7. The method of claim 6, wherein adding at least one second through silicon via in the first region comprises: and adding a second through silicon via with the same size as the first through silicon via in the first area at the same position as the abscissa of the first through silicon via.
8. The method according to claim 2, wherein the method further comprises: determining a second area of the chip, wherein the power consumption of the second area is larger than a second threshold value, and the second area is positioned in the first area, and the area of the second area is smaller than or equal to that of the first area; And adjusting the distribution parameters of the through silicon vias in the second region.
9. The method according to any one of claims 1 to 8, further comprising: And determining the wiring of the chip according to the adjusted distribution parameters of the through silicon vias and the distribution positions of the standard units.
10. A chip, characterized in that it is designed by the method according to any one of claims 1-8, said chip comprising: A substrate; The device layer is positioned on the substrate and comprises a plurality of standard cells; And the silicon through hole penetrates through the substrate and the device layer.

Description

Chip and design method thereof Technical Field The present application relates to the field of chip design, and relates to, but is not limited to, a chip and a design method thereof. Background In recent years, 3D integrated circuits (INTEGRATED CIRCUIT, ICs) have found widespread use. The initial form of the 3DIC is to stack die with the same function from bottom to top to form a 3D stack, then connect the die with bonding wires on both sides, and finally present the die with the appearance of a System-in-Package (SiP). The stacking may be pyramidal, cantilever, or side-by-side. In the related art, a large amount of heat is generated during the operation of the 3D IC, especially, a local area with larger power consumption is easy to generate heat accumulation, so that the temperature is further increased, negative circulation is formed, the performance of the chip is affected, and even the chip is over-temperature disabled. Disclosure of Invention In view of the above, the embodiment of the application provides a chip and a design method thereof. In a first aspect, an embodiment of the present application provides a chip design method, where the method includes: Determining the power consumption of at least two different areas on a chip according to the distribution parameters of a plurality of standard units on the chip; According to the power consumption of the at least two different areas, adjusting the distribution parameters of at least two through silicon vias on the chip; and adjusting the distribution positions of a plurality of standard units on the chip according to the adjusted distribution parameters of the through silicon vias. In some embodiments, the adjusting the distribution parameters of the at least two through silicon vias on the chip according to the power consumption of the at least two different areas includes: determining a first area on the chip where power consumption is greater than a first threshold; And adjusting the distribution parameters of the through silicon vias in the first region. In some embodiments, the adjusting the distribution parameter of the through silicon vias in the first region includes: increasing the cross-sectional area of the through silicon via in the first region, and/or And adding the through silicon vias in the first region. In some embodiments, the increasing the cross-sectional area of the through silicon via in the first region includes: And if the first region comprises at least one through silicon via, increasing the sectional area of at least one through silicon via in the first region. In some embodiments, the adding the through silicon via in the first region includes: and if the first region does not comprise the through silicon vias, adding at least one through silicon via in the first region. In some embodiments, if the first region does not include the through silicon vias, adding at least one through silicon via in the first region includes: Determining a first through silicon via located outside the first region, and an abscissa located within an abscissa range of the first region; at least one second through silicon via is added in the first region. In some embodiments, adding at least one second through silicon via in the first region includes: and adding a second through silicon via with the same size as the first through silicon via in the first area at the same position as the abscissa of the first through silicon via. In some embodiments, the adjusting the distribution positions of the plurality of standard cells on the chip according to the adjusted distribution parameters of the through silicon vias includes: And adjusting the distribution positions of a plurality of standard units on the chip to enable the standard units in the first area to be distributed outside the coverage area of the through silicon vias in the first area. In some embodiments, the method further comprises: determining a second area of the chip, wherein the power consumption of the second area is larger than a second threshold value, and the second area is positioned in the first area, and the area of the second area is smaller than or equal to that of the first area; And adjusting the distribution parameters of the through silicon vias in the second region. In some embodiments, the method further comprises: and adjusting the distribution positions of a plurality of standard units on the chip to enable the standard units in the second area to be distributed outside the coverage area of the through silicon vias in the second area. In some embodiments, the method further comprises: And determining the wiring of the chip according to the adjusted distribution parameters of the through silicon vias and the distribution positions of the standard units. On the other hand, the embodiment of the application also provides a chip, which is designed by adopting any method, and comprises the following steps: A substrate; The device layer is positioned on the substrate a