CN-114121055-B - Memory interconnect architecture system and method

Abstract

The system and method of the present invention is used to efficiently and effectively add processing power to internal memory. In one embodiment, an in-memory Processing (PIM) chip includes a memory array, logic components, and an interconnection network. The memory array is used for storing information. In one exemplary implementation, the memory array includes memory cells and array peripheral components. The logic component can be used to process information stored in the memory array. The interconnection network is to communicatively couple the logic components. The interconnect network can include interconnect lines, and a portion of the interconnect lines are located in a metal layer region that is in turn located over the memory array.

Inventors

• HAN WEI
• FAN XIAOXIN
• NIU DIMIN
• WANG YUHAO
• DUAN LIDE
• ZHENG HONGZHONG
• LI SHUANGCHEN

Assignees

• 阿里巴巴达摩院(杭州)科技有限公司
• 阿里巴巴集团控股有限公司

Dates

Publication Date

20260421

Application Date

20210929

Priority Date

20200929

Claims (14)

1. 1. An in-memory Processing (PIM) chip, the PIM chip comprising: a memory array for storing information, wherein the memory array comprises: memory cell, and An array peripheral component for controlling access to the memory cells; logic means for processing information stored in said memory array, and An interconnect network communicatively coupled to the logic component, wherein the interconnect network includes a first set of interconnect lines and a portion of the first set of interconnect lines is located in a metal region above the memory array.
2. 2. The PIM chip of claim 1, wherein the interconnection network comprises a switch to route information in the interconnection network.
3. 3. The PIM chip of claim 2, wherein the switch is included in a region having the array peripheral component.
4. 4. The PIM chip of claim 2, wherein the switch is configured by other redundant components in the array peripheral component.
5. 5. The PIM chip of claim 2, wherein a second set of interconnect lines communicatively couples the memory cells and array peripheral components, wherein a portion of the second set of interconnect lines are located in metal layer 1, metal layer 2, and metal layer 3, and a portion of the first set of interconnect lines corresponding to the logic components are located in metal layer 4 and metal layer 5.
6. 6. The PIM chip of claim 2, wherein the array peripheral component comprises: A column address decoder for decoding column addresses in the memory array, and And the row address decoder is used for decoding the row address in the memory array.
7. 7. A method of manufacturing a in-memory Processing (PIM) chip, the PIM chip manufacturing method comprising: Forming a memory array in a memory array region of the PIM chip; Forming logic components in a logic region of the PIM chip, wherein the logic components include processing components to process information stored in the memory array, and An interconnect network is formed that communicatively couples the logic components, the interconnect network including interconnect lines, wherein a portion of the interconnect lines are located in a metal layer region above the memory array region.
8. 8. The PIM chip fabrication method of claim 7, further comprising forming a switch in said interconnect network, wherein said switch is coupled to said interconnect lines and is used to route information between said logic components.
9. 9. The PIM chip fabrication method of claim 8, wherein said memory array region comprises a memory cell portion and a memory array peripheral component portion, and said switch is located in the memory array peripheral component portion of said memory array region.
10. 10. The PIM chip fabrication method of claim 8, wherein said switch comprises a multiplexer and a demultiplexer.
11. 11. The PIM chip fabrication method of claim 8, wherein a portion of said interconnect lines for said logic elements are located in metal layers 4 and 5 and a portion of other interconnect lines corresponding to said memory array are located in metal layer 1, metal layer 2, and metal layer 3.
12. 12. An in-memory Processing (PIM) chip, the PIM chip comprising: An internal memory block for storing information; a logic component for processing information stored in the internal memory block, and An interconnect network to communicatively couple the logic components, wherein the interconnect network includes interconnect lines and a portion of the interconnect lines are located in a metal region above the memory block.
13. 13. The PIM chip of claim 12, wherein the interconnect network includes switches in the memory block area and the switches are to route information in the interconnect network.
14. 14. The PIM chip of claim 12, wherein the logic component comprises: a process control component to schedule tasks, configure registers, and process global synchronization, an And an accelerator for accelerating the application process.

Description

Memory interconnect architecture system and method Technical Field The present invention relates to the field of information processing and communication in internal memories. Background Many electronic technologies, such as digital computers, calculators, audio devices, video equipment, and telephone systems, are useful in most business, scientific, educational and recreational fields to improve productivity and reduce costs when analyzing and communicating data and information. Electronic components can be used in many important applications (e.g., medical procedures, vehicle assistance operations, financial applications, etc.), and these activities typically involve storing large amounts of information. The storage and retrieval of information can have a significant impact on system performance. The efficiency and effectiveness of the store operation of the internal memory may depend on the internal memory configuration used. Some conventional systems attempt to add processing power to internal memory. There are many factors that may affect the configuration of the internal memory. Generally toward denser components, but the ability to obtain smaller components in the same semiconductor area has slowed significantly (e.g., according to moore's law, etc.). In addition, implementations with dedicated processors (e.g., CPU, GPU, etc.) and separate internal memory consume a significant amount of energy during access operations, as compared to lower energy consumption in implementations with in-memory Processing (PIM) capabilities. Two-dimensional in-memory processing power (2 DPIM) typically reduces memory access latency, data movement energy, and manufacturing costs. There are also many challenges when attempting to add processing power to an internal memory. Due to DRAM processing, the frequency and performance of 2DPIM is significantly limited by the routing/routing resources. DRAM arrays occupy significant area in PIM but typically do not use top metal layers (e.g., use mainly only 3 of the 5 metal layers). Due to the complexity of SoC designs, the large number of components, and the large memory bandwidth requirements within PIM, complex on-chip interconnects are often required to support the corresponding scalability. However, the increased scalability requirements often place significant stress and difficulty on component and interconnect placement in conventional chip design and architecture approaches. Disclosure of Invention The system and method of the present invention is to efficiently and effectively add processing power to an internal memory. In one embodiment, an in-memory Processing (PIM) chip includes a memory array, logic components, and an interconnection network. The memory array is used for storing information. In one exemplary implementation, a memory array includes memory cells to store information bits and an array peripheral component to control access to the memory cells. The memory cells are located in a first region (e.g., a first portion of a memory chip or die) and the array peripheral components are located in a second region (e.g., a second portion of a memory chip or die). The logic component is included in a third region (e.g., a third portion of the memory chip or die) and can be used to process information stored in the memory array. The interconnection network is to communicatively couple the logic components. The interconnect network may include a first set of interconnect lines, and a portion of the first set of interconnect lines is located in a metal region above the memory array. In one embodiment, the interconnection network includes a switch to route information in the interconnection network. The switch may be included in an area having array peripheral components. In one exemplary implementation, the switch is included in a 2 DPIM. The switch can be configured by other redundant components in the array peripheral components. In one embodiment, a second set of interconnect lines communicatively couples the memory cells and the memory array peripheral components. A portion of the second set of interconnect lines may be located in metal layers 1, 2, and 3, while a portion of the first set of interconnect lines may be located in metal layers 4 and 5. In one exemplary implementation, the internal memory may be configured as Dynamic Random Access Memory (DRAM). The array peripheral component may include a column address decoder to decode a column address in the memory array and a row address decoder to decode a row address in the memory array. In one embodiment, a method of manufacturing a in-memory Processing (PIM) chip includes forming a memory array in a memory array region of the PIM chip, forming logic components in a logic region of the PIM chip, and forming an interconnection network. The logic component may include a processing component. The interconnect network includes interconnect lines and a portion of these interconnect lines are located in a region of t