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CN-114128145-B - Apparatus and method for providing multiple output samples based on multiple input samples

CN114128145BCN 114128145 BCN114128145 BCN 114128145BCN-114128145-B

Abstract

A signal processing apparatus for providing a plurality of output samples (280) based on a plurality of input samples (250), comprising a plurality of processing cores (220) configured to perform processing operations based on respective input samples and associated processing times so as to provide a set (225 a,225 b.) of processing core output samples, and sample combiner logic (210) configured to provide a plurality of output samples from a plurality of sets of processing core output samples of a plurality of processing cores performing processing operations associated with different processing times, wherein the sample combiner logic comprises a hierarchical tree structure having a plurality of hierarchical levels (240 a,240b,240 c) of combiner nodes (230 a,230 b.), wherein each combiner node of a highest hierarchical level is configured to provide a set of combined output samples based on two or more sets of processing core output samples, wherein each combiner node of a given hierarchical level lower than the highest hierarchical level is configured to provide a set of combined output samples based on two or more output samples of an associated combiner node of a higher level, wherein each combiner node is configured to fill a set of combined samples and zero-shifted samples per input per set of input information.

Inventors

  • Christy Volmer

Assignees

  • 爱德万测试公司

Dates

Publication Date
20260512
Application Date
20191223

Claims (20)

  1. 1. A signal processing apparatus for providing a plurality of output samples based on a plurality of input samples, comprising: a plurality of processing cores configured to perform processing operations based on respective input samples and associated processing times to provide a set of processing core output samples, and Sample combiner logic configured to provide the plurality of output samples from a plurality of sets of processing core output samples of the plurality of processing cores, the plurality of processing cores performing processing operations associated with different processing times, Wherein the sample combiner logic comprises a hierarchical tree structure of combiner nodes having a plurality of hierarchical levels, Wherein each combiner node of the highest hierarchical level is configured to provide a set of combined output samples based on two or more sets of processing core output samples, Wherein each combiner node of a given hierarchical level lower than the highest hierarchical level is configured to provide a set of combined output samples based on two or more sets of output samples of associated combiner nodes of higher hierarchical levels, Wherein each combiner node is configured to combine respective sets of input samples, Wherein each set of input samples becomes shifted and/or zero-padded in accordance with time information associated with the input sample set.
  2. 2. The signal processing device of claim 1, wherein the target output sample rate of the output samples is lower than or equal to the input sample rate of the input samples.
  3. 3. The signal processing apparatus according to claim 1 or 2, comprising a time accumulator configured to: tracking global processing time, and The transmission of a plurality of output samples from an output register and/or accumulator logically coupled to the sample combiner is triggered whenever the global processing time overflows a predetermined multiple of the sampling period of the output samples.
  4. 4. The signal processing device according to claim 1 or 2, Wherein the number of samples in the input sample set of combiner nodes in the same hierarchical level is the same, and/or Wherein the number of samples in the output sample set of the plurality of combiner nodes in the same hierarchical level is the same.
  5. 5. A signal processing apparatus as claimed in claim 1 or 2, wherein the number of samples in a given set of output samples of a combiner node is greater than the number of samples in each set of input samples provided to the given combiner node by a next higher hierarchical level combiner node or by the processing core.
  6. 6. The signal processing apparatus of claim 1 or 2, wherein the sample combiner logic is configured such that the number of samples provided to the combiner nodes by respective combiner nodes of a next higher hierarchical level as input samples increases progressively with decreasing hierarchical level.
  7. 7. Signal processing apparatus according to claim 1 or 2, wherein the number of input samples and/or output samples of each combiner node is based on the number of samples of the output sample set of a single processing core and/or on the hierarchical level of each combiner node and/or on the factorization of the number of processing cores into integer factors.
  8. 8. A signal processing apparatus as claimed in claim 1 or 2, wherein the number of sets of input samples for each combiner node is dependent on a factorisation which breaks down the number of processing cores into integer factors.
  9. 9. The signal processing apparatus according to claim 1 or 2, wherein the number of input sample sets of each combiner node of a given hierarchical level is equal to Wherein the method comprises the steps of Integer factors representing P, according to Where P represents the number of processing cores, H represents the total number of factors in the selected integer factorization, and H represents the hierarchical level of each combiner node.
  10. 10. The signal processing apparatus of claim 1 or 2, wherein the number of samples in each input sample set of the respective combiner node is based on the following equation: Wherein the method comprises the steps of Representing the number of samples in each input sample set, Representing the number of input sample sets for each combiner node at a given hierarchical level, Integer factors representing P, according to , Wherein the method comprises the steps of P represents the number of processing cores and, H represents the total number of factors in the selected integer factorization, H represents the hierarchical level of each combiner node, and M represents the number of samples of the output sample set of a single processing core.
  11. 11. The signal processing apparatus according to claim 1 or 2, wherein the number of output samples of each combiner node is based on the following equation: Wherein the method comprises the steps of Indicating the number of output samples that are to be taken, Integer factors representing P, according to , Wherein the method comprises the steps of P represents the number of processing cores and, H represents the total number of factors in the selected integer factorization, H represents the hierarchical level of each combiner node, and M represents the number of samples of the output sample set of a single processing core.
  12. 12. The signal processing apparatus of claim 1 or 2, wherein each combiner node in each hierarchical level of the sample combiner logic is configured to provide a set of combined output samples, Wherein the set of combined output samples is a combination of the set of input samples, Wherein the signal processing means is configured to determine how many samples the input sample set is shifted relative to each other before combining in accordance with the following relationship: a relationship between time information associated with the input sample set.
  13. 13. The signal processing apparatus of claim 1 or 2, wherein each combiner node in each hierarchical level of the sample combiner logic is configured to provide the set of combined output samples by summing appropriately zero-padded versions of the set of input samples, Wherein the amount and location of the padding of a particular set of input samples depends on time information associated with the set of input samples.
  14. 14. The signal processing apparatus according to claim 1 or 2, wherein the combiner node of the highest hierarchical level is configured to: Each time information associated with each input sample set is received, wherein each time information corresponds to a processing time associated with each input sample set.
  15. 15. The signal processing apparatus of claim 1 or 2, wherein the processing cores are configured to determine the processing function using fractional parts of each processing time associated with each processing core, and Wherein the signal processing means is configured to use an integer part of the respective processing time associated with the respective processing core as time information associated with the respective set of input samples provided to the respective combiner node of the highest hierarchical level.
  16. 16. The signal processing apparatus of claim 1 or 2, wherein each combiner node at each hierarchical level is configured to assign time information to the combined output samples based on time information associated with the set of input samples.
  17. 17. The signal processing apparatus of claim 1 or 2, wherein the time information assigned to the combined output sample is equal to the time information associated with one of the input sample sets.
  18. 18. The signal processing apparatus according to claim 1 or 2, comprising an output register configured to store a plurality of output samples.
  19. 19. The signal processing apparatus of claim 18, wherein the output register is configured to accumulate and/or integrate values of output samples.
  20. 20. A signal processing apparatus according to claim 3, wherein the output accumulator comprises a shift register.

Description

Apparatus and method for providing multiple output samples based on multiple input samples Technical Field Embodiments in accordance with the invention relate to digital signal processing. Further embodiments in accordance with the invention relate to real-time waveform processing on a digital signal processor (DIGITAL SIGNAL processor, DSP). More particularly, it relates to real-time waveform processing on a DSP, where the rate of processed data is higher than the clock speed of the DSP, thus employing a parallel data processing architecture. Embodiments of the present invention relate to a parallel decimating digital convolver. Background Decimation (decimation) describes a down-sampling process to produce an approximation of the sequence that would have been obtained by sampling the signal at a lower rate. Meaning that the output sampling rate is generally lower than or equal to the input sampling rate. The decimator or decimator convolves the input waveform given with equidistant sampling with a continuous time impulse response and produces the result of this operation at its output at a sampling rate that is less than or equal to the input rate. The continuous time impulse response is stretched in time in proportion to the sample rate ratio. With a properly selected impulse response, the decimator can be designed to suppress spectral content in the input waveform that would otherwise produce unwanted aliasing effects at the output sampling rate. The decimator exhibits an algorithmic architecture suitable for convenient implementation on an Application SPECIFIC INTEGRATED Circuit (ASIC) or field-programmable gate array (FPGA) GATE ARRAY. The conventional decimator may be implemented as a transposed farrow structure (transposed Farrow structure). The impulse response of the transposed-farrow structure is described in terms of a piecewise polynomial. Implementations of conventional operations for performing decimated convolutions or decimated digital convolutions on a sequential DSP are proposed by Babic and Hentschel and summarized below. The time accumulator accumulates fractional samples in delta increments in half-open intervals [0:1 ]. The decimation ratio is 1/Δ/, where Δ is within half-open interval [0:1 ]. When the time accumulator overflows, the decimator transmits one output sample and moves the output sample by one position in the output accumulator. Within the output accumulator, there are multiple output samples in preparation. The output accumulator accumulates or integrates the results of a plurality of so-called dot-cores. Each of the point kernels calculates a dot product or scalar vector product between the vector of coefficients and the corresponding output vector of the polynomial evaluator. The coefficients of the point kernels determine the continuous-time convolution kernel in a piecewise polynomial fashion and thus also the response of the decimator. The number of output samples, or the number of corresponding point kernels, M, of the plurality of output samples is referred to as the support of the method Luo Chouqu machine, while the number of coefficients, N, in the coefficient vector is the degree of the method Luo Chouqu machine. The polynomial evaluator multiplies the input samples by successive powers of accumulated fractional time 0, 1. As a result of the accumulation process, the amplitude of the output waveform is scaled by 1/Δt. To match the output amplitude to the input or input amplitude, each output sample is multiplied by Δt. Traditional farrow implementations process one sample at a time, i.e. its parallelism is 1. Whenever the sampling rate is higher than the clock rate of the digital signal processor, parallel processing operations (e.g., on a common set of samples) need to be performed while keeping the effort of combining the samples reasonably small. This object is solved by the subject matter of the independent claims. Disclosure of Invention An embodiment of the invention (see e.g. claim 1) is a digital signal processing apparatus, such as a decimator or a decimator convolver, for providing a plurality of output samples, or output values, e.g. P output samples, in parallel based on a plurality of input samples or sets of input values, e.g. input values of a processing core. The digital signal processing apparatus comprises a plurality of processing cores or modified transposed normal cores configured to perform processing operations, such as decimating operations or decimating digital convolution operations based on respective input samples and associated processing times, in order to provide a set of processing core output samples, such as M processing core output samples per processing core. The digital signal processing apparatus also includes sample combiner logic or structure configured to provide a plurality of output samples from a plurality of sets of processing cores of the plurality of processing cores, such as a decimator core or a method Luo Chouqu