CN-114141767-B - Integrated structure of IGZO transistor and GaN HEMT gate control circuit and preparation method thereof

Abstract

The invention discloses an integrated structure of an IGZO transistor and a GaN HEMT gate control circuit and a preparation method thereof, which relate to the technical field of semiconductors, wherein the integrated structure is divided into two parts, one part is a GaN HEMT structure, the other part is an IGZO transistor, the two parts are grown on a substrate, the invention provides an integrated gate control circuit structure which is based on growth of a GaN HEMT, an IGZO transistor and a diamond substrate, wherein the IGZO transistor is used for controlling a high-power GaN HEMT and is integrated on a substrate, the GaN HEMT device is a high-power device, and how to dissipate heat and ensure normal operation of the GaN HEMT device is a research hot spot problem. The diamond material has good heat conducting performance, and can be introduced as a substrate to better enhance the heat dissipation capability of devices and circuits.

Inventors

• LI YANZUO
• CHEN XING
• WANG DONG
• WU YONG
• HUANG YONG
• CHEN YAO
• LIN CHANGZHI
• Qiu Huiyan
• XIE YUFENG

Assignees

• 西安电子科技大学芜湖研究院

Dates

Publication Date

20260505

Application Date

20211126

Claims (4)

1. 1. An integrated structure of an IGZO transistor and a GaN HEMT gate control circuit is characterized in that the integrated structure is specifically divided into two parts, one part is a GaN HEMT structure and the other part is an IGZO transistor, and the two parts are grown on a substrate (101); the GaN HEMT structure is sequentially provided with a substrate (101), an AlGaN buffer layer (102), a GaN layer (103), an AlN layer (104), an Al 0.2 Ga 0.8 N layer (105), an AlGaN layer (106), a first SiN layer (107), a source drain electrode (108), an Al 2 O 3 medium layer (109) and a GaN HEMT gate end (110) from bottom to top; A substrate (101), a SiO 2 layer (111), an ITO layer (112) (serving as a source end, a drain end and a gate end), an Al 2 O 3 buffer layer (113), an IGZO base layer (114), an IGZO Boost layer (115), an HfO 2 dielectric layer (116) and an IGZO transistor gate end (117) are sequentially arranged in the IGZO transistor from bottom to top; After the two parts are manufactured, a second SiN layer (118), an extraction electrode (119) connected with the source-drain electrode (107), an external metal wire (120) connected with the GaN HEMT source-drain extraction electrode (119), a first extraction metal wire (121) connected with the GaN HEMT gate end (110), a second extraction metal wire (122) connected with the ITO layer (112), a third metal extraction wire (123), a first metal wire (124) and a second metal wire (125) respectively connected with the GaN HEMT gate end extraction metal wire (121) and the IGZO transistor source-drain extraction metal wire (122) are further arranged on the two parts.
2. 2. The integrated structure of an IGZO transistor and GaN HEMT gate control circuit according to claim 1, wherein said substrate (101) is made of diamond material of epitaxial GaN film with a size range of 2-8inch.
3. 3. The integrated structure of an IGZO transistor and GaN HEMT gate control circuit of claim 1, wherein a layer of SiN is grown on a substrate (101), and then etched in a corresponding GaN HEMT device location area to form a recess, and a GaN HEMT device is fabricated in the recess.
4. 4. The method for manufacturing the integrated structure of the IGZO transistor and the GaN HEMT gate control circuit according to claim 1, comprising the steps of: (1) Growing a thicker SiN layer (118) on the substrate (101), and then etching the corresponding GaN HEMT device position area to form a concave hole; (2) On the basis of the structure, an AlGaN buffer layer (102) is grown by adopting a metal organic source chemical vapor deposition method; (3) A GaN buffer layer (103) is formed by unintentional doping growth on the basis of the structure by adopting a metal organic source chemical vapor deposition method or other methods, and the thickness of the GaN buffer layer is 100nm-10um; (4) An AlN layer (104) is formed by unintended doped growth on the basis of the structure by adopting a metal organic source chemical vapor deposition method; (5) An Al 0.2 Ga 0.8 N layer (105) is formed by unintended doped growth on the basis of the structure by adopting a metal organic source chemical vapor deposition method; (6) An AlGaN layer (106) is formed by unintended doped growth on the basis of the structure by adopting a metal organic source chemical vapor deposition method; (7) Etching is carried out on the AlGaN layer (106), concave holes are reserved, and SiO 2 is grown in the concave holes by PECVD so as to keep the positions of the gate dielectric and the gate electrode; (8) Growing a first SiN layer (107) on the basis of the structure by adopting a PECVD method, wherein the thickness of the first SiN layer is 100nm; (9) An electrode of ohmic contact is manufactured by magnetron sputtering and is used as an electrode of a source end and a drain end, meanwhile, on the basis of the concave hole position of an original AlGaN layer (106), a first SiN layer (107) is etched, a plurality of concave holes with the size larger than that of the original concave holes are reserved, and SiO 2 is grown in the larger concave holes by adopting a PECVD method so as to keep the positions of a gate medium and the gate electrode; (10) Etching SiO 2 , growing a gate Al 2 O 3 dielectric layer (109) by ALD, and manufacturing a GaN HEMT gate end (110) on the basis; (11) Growing a second SiN layer (118) on the basis of the structure by adopting a PECVD method, wherein the thickness of the second SiN layer is 300nm; (12) Etching the Al 2 O 3 dielectric layer (109), the first SiN layer (107) and the second SiN layer (118) to form a through hole, depositing metals such as Ti/Al/Ni/Au, leading out source and drain electrodes, leaving Pad points above the first SiN layer (107), etching the first SiN layer (107) in the corresponding areas of the gate electrode (110) and the source and drain electrodes (108), depositing metals such as Ti/Al/Ni/Au, leading out gate electrode metal (121) and source and drain electrode metal (119), and growing the second SiN layer (118) upwards by using a PECVD method; (13) Etching at a position corresponding to the IGZO transistor, etching a concave hole from the originally grown second SiN layer (118), and manufacturing the IGZO transistor in the concave hole region; (14) Etching In the channel region to form concave holes, and forming an IGZO base layer (114) at the left position for manufacturing an In 0.52 Ga 0.29 Zn 0.19 O and an IGZO Boost layer (115) In 0.82 Ga 0.08 Zn 0.10 O, and growing a SiO 2 masking layer In the surrounding region to ensure that the IGZO base layer (114) and the IGZO Boost layer (115) are manufactured In the region nearby the channel; (15) Removing the surrounding redundant SiO 2 masking layer, and then growing the Al 2 O 3 buffer layer (113); (16) On the basis of the structure, the HfO 2 dielectric layer (116) is grown by ALD, and the thickness is 50nm; (17) Etching the corresponding channel region to a certain extent, leaving a pit, wherein the grid end (117) of the IGZO transistor is an ITO medium, and growing by ALD, and manufacturing a T-shaped grid due to the reserved pit; (18) Etching the HfO 2 dielectric layer (116) and the Al 2 O 3 buffer layer (113) to form a through hole, manufacturing Ti/Al/Ni/Au multilayer metal, manufacturing a second lead-out metal wire (122), ensuring that the second SiN layers (118) of the two devices are near the same height, manufacturing a metal wire (124) with the width capable of meeting the maximum current drive at the moment, and connecting the source end of the IGZO transistor and the drain end of the GaN HEMT; (19) On the basis, continuing to grow the second SiN layer (118) as a passivation layer and an isolation layer for protecting the device; (20) Etching is carried out on two ends of a source electrode and a drain electrode of the GaN HEMT and corresponding areas of the drain electrode of the IGZO transistor to form concave holes, metal electrodes are manufactured in the concave holes, and an external metal wire (120) connected with the source electrode and the drain electrode of the GaN HEMT and a second metal wire (125) led out from the drain electrode of the IGZO transistor are manufactured, wherein the external metal wire (120) connected with the source electrode and the drain electrode of the GaN HEMT and the first metal wire (124) are not overlapped in a three-dimensional space.

Description

Integrated structure of IGZO transistor and GaN HEMT gate control circuit and preparation method thereof Technical Field The invention belongs to the technical field of semiconductors, and particularly relates to an integrated structure of an IGZO transistor and a GaN HEMT gate control circuit and a preparation method of the integrated structure. Background Third generation semiconductor materials (Wide Band Gap Semiconductor, WBGS for short) with wide forbidden bands like gallium nitride (GaN), diamond and silicon carbide (SiC). Among them, gallium nitride (GaN) has a wide band gap, a direct band gap, a high breakdown field strength, a low dielectric constant, a high saturated electron drift velocity, a good irradiation resistance and a good chemical stability, and thus becomes a hot spot for research and application. AlGaN/GaN HEMT devices have many advantages, including mainly high breakdown voltage, low on-resistance, etc., and are therefore considered to be excellent power switching devices or power electronics in the industry. The GaN device has a plurality of advantages under the application conditions of high temperature, high power, high frequency, irradiation and the like. Therefore, the gallium nitride material and the circuit thereof are key basic materials of high-precision technologies such as microelectronics, power electronics, photoelectrons and the like, and have certain influence on the fields of national defense industry, information technology industry and the like. In the display field, IGZO technology has several advantages over a-Si amorphous silicon technology. First is the high mobility of IGZO transistors, which is around 10cm 2/Vs, at least ten times more than a-Si amorphous silicon, which is the basis for high frequency gated switching devices. The IGZO has good stability under illumination, and has the advantages of good uniformity, high transparency and simple manufacturing process. There is also a very important aspect that the turn-off effect of the IGZO transistor is very good, which is an important guarantee for reducing the power consumption of the control circuit. Compared to Low Temperature Polysilicon (LTPS), IGZO has only one ten thousandth of its leakage rate. If the control terminal of the control circuit is a mobile small-capacity direct current power supply, IGZO transistors will have good advantages in terms of low power consumption as the control terminal circuit. The general gallium nitride power device adopts silicon as the material of the epitaxial substrate, but the heat conduction performance of the silicon material is not ideal, and the development and application of the gallium nitride power device are hindered to a certain extent. In the prior art, polycrystalline diamond and gallium nitride-based power devices can be bonded, so that the heat dissipation performance of the whole device is improved. In controlling high power GaN HEMT devices with low voltage signals, si-based CMOS circuits are typically used. Si-based integrated circuits have performed very well in the semiconductor industry over the years, taking into account all aspects, and are therefore very widely used in the integrated circuit field and have a large share in the market. However, si-based integrated circuits have their limitations and in some respects do not perform well enough as compound semiconductors. In the prior art, there are few IGZO transistors using double channels in a low voltage control circuit. IGZO transistors are used in the display field, but they have the advantage of good turn-off effect and low driving power, which makes it possible to use them in driving switches for low power circuits driving high power circuits. Therefore, how to combine and apply the two circuit structures to control the high-power GaN HEMT is a problem that needs to be solved at present. Disclosure of Invention The invention aims to provide an integrated structure of an IGZO transistor and a GaN HEMT gate control circuit and a preparation method thereof, so as to solve the defects caused by the prior art. An integrated structure of an IGZO transistor and a GaN HEMT gate control circuit is specifically divided into two parts, wherein one part is a GaN HEMT structure, the other part is an IGZO transistor, and the two parts are grown on a substrate (101); The GaN HEMT structure is sequentially provided with a substrate, an AlGaN buffer layer, a GaN layer, an AlN layer, an Al 0.2Ga0.8 N layer, an AlGaN layer, a first SiN layer, a source drain electrode, an Al 2O3 medium layer and a GaN HEMT gate end from bottom to top; A substrate, a SiO 2 layer, an ITO layer (serving as a source end, a drain end and a gate end), an Al 2O3 buffer layer, an IGZO base layer, an IGZO Boost layer, an HfO 2 dielectric layer and an IGZO transistor gate end are sequentially arranged in the IGZO transistor from bottom to top; after the two parts are manufactured, a second SiN layer 118, an extraction electrode connected