CN-114153497-B - Multi-port register file based on single-ended voltage sensitive amplifier structure

CN114153497BCN 114153497 BCN114153497 BCN 114153497BCN-114153497-B

Abstract

The invention relates to a multi-port register file based on a single-ended voltage sense amplifier structure, which comprises a storage unit array, a read address decoder, a write address decoder, a read data path and a write data path, wherein the storage unit array is formed by cross-coupled inverter pairs and is provided with a plurality of write ports and a plurality of read ports, the read address decoder and the write address decoder are all realized by adopting full static logic, the read data path adopts the single-ended voltage sense amplifier and an RS latch structure to realize read operation, and the write data path adopts a mode of dividing write bit lines to carry out block driving of write data. The invention improves the performance and reduces the dynamic power consumption.

Inventors

FANG HUA
ZHAO XIN

Assignees

上海高性能集成电路设计中心
上海高性能集成电路设计中心

Dates

Publication Date: 20260421
Application Date: 20211130
Priority Date: 20211124

Claims (6)

1. A multi-port register file based on a single-ended voltage sense amplifier structure is characterized by comprising a storage unit array, a read address decoder, a write address decoder, a read data path and a write data path, wherein the storage unit array is formed by cross-coupled inverter pairs and is provided with a plurality of write ports and a plurality of read ports, the read address decoder and the write address decoder are all realized by adopting full static logic, the read data path adopts the single-ended voltage sense amplifier and RS latch structure to realize read operation, the purpose of quickly reading effective data is achieved by amplifying swing signals, and the write data path adopts a mode of dividing write bit lines to carry out block driving of write data; The read address decoder comprises a dynamic differential read address generation module, a dynamic read enabling narrow pulse width generation module, a static logic full decoding module, a pre-charge clock and an amplifier enabling generation module, wherein the dynamic differential read address generation module generates a differential dynamic address signal through positive edge clock gating Latch for subsequent read address decoding, the dynamic read enabling narrow pulse width generation module generates dynamic read enabling through positive edge clock gating Latch, the narrow pulse width reading enabling is generated through a pulse signal generator and participates in subsequent read address decoding, the static logic full decoding module completes full decoding of the differential dynamic address signal and the narrow pulse width reading enabling through static logic, finally generates a narrow pulse width read word line, starts any item to perform read operation of a storage array, the pre-charge clock and the amplifier enabling generation module generates an input read enabling signal through positive edge clock gating Latch, and the pre-charge signal generates a sensitive amplifier enabling signal through a delay gating unit.
2. The multi-port register file based on the single-ended voltage sense amplifier architecture of claim 1, wherein each write port of the memory cell array is a single-ended write port consisting of 3 transistors for ensuring strong '0' write storage node positive and negative points to achieve write '0' and write '1' operations.
3. The multi-port register file based on a single-ended voltage sense amplifier architecture of claim 1, wherein each read port of the memory cell array is a pull-down architecture single-ended read port comprised of 2 transistors, structurally isolated from the memory node, and wherein the plurality of read ports are equally suspended at the positive and negative points of the memory node.
4. The multi-port register file based on the single-ended voltage sense amplifier structure of claim 1, wherein the read data path comprises a single-ended voltage sense amplifier and an RS latch, the single-ended voltage sense amplifier is composed of a reference voltage generator and a high-resolution voltage latch type voltage sense amplifier, one end of a differential input signal of the high-resolution voltage latch type voltage sense amplifier is connected with a read port bit line, the other end of the differential input signal of the high-resolution voltage latch type voltage sense amplifier is connected with the reference voltage generator, the RS latch is built by a static NOR gate, and the read pulse signal is stretched and kept until the next read operation by matching with the single-ended voltage sense amplifier.
5. The multi-port register file based on the single-ended voltage sense amplifier architecture of claim 1, wherein the single-ended voltage sense amplifier implements a fixed reference voltage in a charge sharing manner, and in combination with a discharging condition on a bit line, a voltage swing difference is formed, and an output is amplified by the single-ended voltage sense amplifier for performing a read 0 or read 1 operation.
6. The multi-port register file based on the single-ended voltage sensitive amplifier structure according to claim 1, wherein the write address decoder comprises a dynamic differential write address generation module, a dynamic write enable narrow pulse width generation module and a static logic full decoding module, the dynamic differential write address generation module latches an input write address by a register for one beat, then generates a differential dynamic address signal through a negative edge clock gating Latch for subsequent write address decoding, the dynamic write enable narrow pulse width generation module latches the input write enable by the register for one beat, then generates the dynamic write enable through the negative edge clock gating Latch, generates the narrow pulse width write enable through a pulse signal generator and participates in subsequent write address decoding, and the static logic full decoding module completes full decoding of the differential dynamic address signal and the narrow write enable through the static logic, finally generates a write word line, opens any one entry and performs write operation of the memory array.

Description

Multi-port register file based on single-ended voltage sensitive amplifier structure Technical Field The invention relates to the technical field of multi-port register files of microprocessors, in particular to a multi-port register file based on a single-ended voltage sensitive amplifier structure. Background A register file (REGISTER FILE, RF) in a superscalar microprocessor requires multiple ports for simultaneous read and write operations. To meet performance requirements, it is often necessary to customize a memory array (bitcell) of multiple read and write ports to build up an implementation, and to employ a dynamic domino architecture to enhance read data performance. However, as processor architectures further improve, the number of register file ports and the number of entries further increases, while meeting the requirements of the system, resulting in constraints on the performance and physical availability of the register file itself. To improve the performance of a processor, a more optimal register file design method must be provided to solve the problems of multiple ports and multiple entries. With the increase of the number of ports, the area of bitcell is larger and larger, the line load of a word line (word line) is further influenced, the resistance of a bottom line is deteriorated, the layout design difficulty is improved, the number of entries is increased, the load of a read bit line (bit line) is larger and larger, and the design requirement cannot be met due to the structure of a two-stage dynamic line or a word line. Aiming at the situation, the method of multiplexing array split ports is generally adopted in the industry to reduce the design difficulty of a single array, but more array area is needed to be spent, the difficulty of upper layer design is increased, and the design method of time division multiplexing compression port number is adopted, so that multiple times of reading and writing are completed in one beat, but more complicated control design is introduced, the single performance of a register file is influenced, the reliability is brought, and the benefit is not obvious. Therefore, a more efficient design approach is needed to meet application requirements. Disclosure of Invention The invention aims to solve the technical problem of providing a multi-port register file realization method based on a single-end voltage sensitive amplifier structure, which meets the requirements of simultaneous reading and writing of a plurality of ports and the requirements of realizing reading and writing operation in one beat, realizes the design of the multi-port high-performance register file, improves the performance and reduces the dynamic power consumption. The technical scheme includes that the multi-port register file based on the single-ended voltage sense amplifier structure comprises a storage unit array, a read address decoder, a write address decoder, a read data path and a write data path, wherein the storage unit array is formed by cross-coupled inverter pairs and is provided with a plurality of write ports and a plurality of read ports, the read address decoder and the write address decoder are all realized by adopting all-static logic, the read data path adopts the single-ended voltage sense amplifier and RS latch structure to realize read operation, the purpose of quickly reading effective data is achieved by amplifying swing signals, and the write data path adopts a mode of dividing write bit lines to carry out block driving of write data. Each write port of the memory cell array is a single-ended write port consisting of 3 transistors, and is used for ensuring that strong '0' is written into a positive point and a negative point of a memory node to realize write '0' and write '1' operations. Each read port of the memory cell array is a single-ended read port of a pull-down structure consisting of 2 transistors, is structurally isolated from a memory node, and is averagely hung at a positive point and a negative point of the memory node. The read address decoder comprises a dynamic differential read address generation module, a dynamic read enabling narrow pulse width generation module, a static logic full decoding module, a pre-charge clock and an amplifier enabling generation module, wherein the dynamic differential read address generation module generates a differential dynamic address signal through positive edge clock gating Latch for subsequent read address decoding, the dynamic read enabling narrow pulse width generation module generates dynamic read enabling through positive edge clock gating Latch, the narrow pulse width reading enabling is generated through a pulse signal generator and participates in subsequent read address decoding, the static logic full decoding module completes full decoding of the differential dynamic address signal and the narrow pulse width reading enabling through static logic, finally generates a narrow pulse width read word line