CN-114203234-B - Semiconductor memory device with a memory cell having a memory cell with a memory cell having a memory cell

CN114203234BCN 114203234 BCN114203234 BCN 114203234BCN-114203234-B

Abstract

The embodiment provides a semiconductor memory device capable of setting a selection gate line to a desired voltage at a high speed. The semiconductor memory device of the embodiment includes a plurality of memory cells, a word line connected to gates of the plurality of memory cells, a bit line electrically connected to one end of the plurality of memory cells via a plurality of select gate transistors connected to one end of the plurality of memory cells, 2 external select gate lines connected to gates of the 2 select gate transistors at both ends of a block, 1 or more internal select gate lines connected to gates of the 1 or more select gate transistors other than both ends of the block, and a voltage generation circuit capable of individually controlling voltage supply to the external select gate lines and the internal select gate lines when reading data recorded in the plurality of memory cells.

Inventors

Bosom friend of China and Sichuan
KATO MITSUSHI
HASHIMOTO TOSHIFUMI

Assignees

铠侠股份有限公司
铠侠股份有限公司

Dates

Publication Date: 20260421
Application Date: 20210122
Priority Date: 20200917

Claims (9)

1. A semiconductor memory device includes: A plurality of memory cells; A word line connected to gates of the plurality of memory cells; Bit lines electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the plurality of select gate transistors including 2 external select gate transistors and more than 1 internal select gate transistors located between the 2 external select gate transistors; 2 external select gate lines connected to the gates of the 2 external select gate transistors, respectively; More than 2 internal select gate lines respectively connected to the gates of the more than 1 internal select gate transistors, and And a voltage generating circuit that supplies a1 st voltage to the external select gate line and a 2 nd voltage to the internal select gate line independently when reading out data recorded in the plurality of memory cells.
2. The semiconductor memory device according to claim 1, wherein The voltage rising rates of the 1 st voltage and the 2 nd voltage are controlled to be different.
3. The semiconductor memory device according to claim 2, wherein The voltage generating circuit includes an external select gate line driver for supplying a voltage to the external select gate line, and an internal select gate line driver for supplying a voltage to the internal select gate line; The resistance value of the voltage supply path of the external select gate line driver is larger than the resistance value of the voltage supply path of the internal select gate line driver.
4. The semiconductor memory device according to claim 1, wherein The application periods of overdrive voltages supplied to the external select gate lines and the internal select gate lines are controlled to be different.
5. The semiconductor memory device according to claim 4, wherein The voltage generation circuit comprises an external selection gate line voltage generation circuit for generating a voltage supplied to the external selection gate line, and an internal selection gate line voltage generation circuit for generating a voltage supplied to the internal selection gate line; The overdrive voltage of the external select gate line voltage generating circuit is applied for a shorter period than that of the internal select gate line voltage generating circuit.
6. The semiconductor memory device according to claim 1, wherein The voltage generating circuit has a driver for an external select gate line that generates a voltage supplied to the external select gate line, The external select gate line driver controls voltage supply according to the number of external select gate lines corresponding to memory cells that are not read targets among the plurality of memory cells.
7. The semiconductor memory device according to claim 6, wherein The external select gate line driver changes the resistance value on the voltage supply path between 1 and 2 for the number of external select gate lines corresponding to the memory cells that are not the read target.
8. The semiconductor memory device according to claim 1, wherein The voltage generating circuit has a driver for an internal select gate line that generates a voltage supplied to the internal select gate line, The internal select gate line driver controls voltage supply according to the number of internal select gate lines corresponding to memory cells that are not read targets among the plurality of memory cells.
9. The semiconductor memory device according to claim 8, wherein In the driver for internal select gate lines, the resistance value on the voltage supply path decreases as the number of internal select gate lines corresponding to the memory cells that are not the read target increases.

Description

Semiconductor memory device with a memory cell having a memory cell with a memory cell having a memory cell [ Related application ] The present application enjoys priority over Japanese patent application No. 2020-156299 (application date: 9/17/2020). The present application includes all of the content of the base application by reference to the base application. Technical Field Embodiments of the present invention relate to a semiconductor memory device. Background In recent years, semiconductor memory devices such as NAND flash memories tend to be three-dimensionally structured due to demands for miniaturization And large capacity. In addition, in a NAND-type flash memory, a memory cell transistor may be configured as an SLC (SINGLE LEVEL CELL, single layer unit) capable of storing 1 bit (2 value) data, or may be configured as an MLC (Multi LEVEL CELL, multi layer unit) capable of storing 2 bits (4 value) data, TLC (TRIPLE LEVEL CELL, three layer unit) capable of storing 3 bits (8 value) data, or QLC (Quad LEVEL CELL, four layer unit) capable of storing 4 bits (16 value) data. In reading out data from such a memory cell transistor, it is necessary to prepare a plurality of voltages and switch the voltages supplied to the memory cell transistor. Therefore, in order to increase the read speed, it is necessary to speed up the transition to the desired target voltage. Disclosure of Invention The present embodiment provides a semiconductor memory device capable of setting a selection gate line to a desired voltage at a high speed. The semiconductor memory device of the embodiment includes a plurality of memory cells, a word line connected to gates of the plurality of memory cells, a bit line electrically connected to one end of the plurality of memory cells via a plurality of select gate transistors connected to one end of the plurality of memory cells, 2 external select gate lines connected to gates of the 2 select gate transistors at both ends of a block, 1 or more internal select gate lines connected to gates of the 1 or more select gate transistors other than both ends of the block, and a voltage generation circuit capable of individually controlling voltage supply to the external select gate lines and the internal select gate lines when reading data recorded in the plurality of memory cells. Drawings Fig. 1 is a block diagram showing an exemplary configuration of a memory system according to an embodiment. Fig. 2 is a block diagram showing a configuration example of a nonvolatile memory according to an embodiment. Fig. 3 is a diagram showing a block configuration example of the NAND memory cell array 23 having a three-dimensional structure. Fig. 4 is a diagram showing potential changes of each wiring in the writing operation (programming operation). Fig. 5 is an explanatory diagram for explaining each select gate line SGD in1 block BLK. Fig. 6 is a diagram showing time on the horizontal axis and voltage on the vertical axis for explanation USTRDIS. Fig. 7 is a diagram showing potential changes of each wiring in the writing operation (programming operation). Fig. 8 is a diagram for explaining a problem in the USTRDIS period by the same expression as fig. 6. Fig. 9 is a block diagram showing a partial configuration of the voltage generation circuit 28. Fig. 10 is a block diagram showing an example of the configuration of the row decoder 25. Fig. 11 is a circuit diagram showing an example of a specific configuration of the drivers 42 to 45 in fig. 9. Fig. 12 is a circuit diagram showing an example of a specific configuration of the MUX (inner) 46 in fig. 9. Fig. 13 is a circuit diagram showing an example of a specific configuration of the MUX (outer) 47 in fig. 9. Fig. 14 is a diagram for explaining the effect of the embodiment. Fig. 15 is a circuit diagram showing an sgd_usel (outer) driver used in embodiment 2 of the present invention. Fig. 16 is an explanatory diagram for explaining an operation of the embodiment. Fig. 17 is an explanatory diagram for explaining an operation of the embodiment. Fig. 18 is a circuit diagram showing an sgd_usel (inner) driver. Fig. 19 is a block diagram showing embodiment 3 of the present invention. Fig. 20 is a graph showing the voltage changes of the external select gate line SGD (outer) and the internal select gate line SGD (inner) in the USTRDIS period by taking time on the horizontal axis and taking voltage on the vertical axis. Detailed Description Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. (Embodiment 1) In this embodiment, the overdrive voltage higher than the target voltage targeted by the voltage generating circuit can be supplied, and the resistance value of the overdrive voltage supplying circuit is changed according to the type of the select gate line, so that the change in the voltage applied to the select gate line can be made uniform regardless of the type of the select gate line,