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CN-114242616-B - Process fault processing method and semiconductor process equipment

CN114242616BCN 114242616 BCN114242616 BCN 114242616BCN-114242616-B

Abstract

The embodiment of the invention provides a process fault processing method and semiconductor process equipment, and the method comprises the steps of determining that a failed target chamber module is a serial module or a parallel module when a process task is executed, adjusting transmission path information of an associated wafer which needs to pass through the target chamber module if the target chamber module is the serial module, generating a new dispatching action sequence according to the adjusted transmission path information, transmitting a detained wafer detained in the target chamber module to another parallel module corresponding to the target chamber module if the target chamber module is the parallel module, generating a new dispatching action sequence aiming at the detained wafer, and continuously executing the process task according to the newly generated dispatching action sequence. According to the embodiment of the invention, the automation level of the equipment can be improved and the complexity of manually processing fault exception can be reduced by realizing the automation flow of Job exception processing through scheduling optimization.

Inventors

  • XIANG HUIFENG

Assignees

  • 西安北方华创微电子装备有限公司
  • 北京北方华创微电子装备有限公司

Dates

Publication Date
20260512
Application Date
20211129

Claims (7)

  1. 1. A process fault handling method for a semiconductor processing tool including a plurality of chamber modules for performing process tasks on a wafer, the plurality of chamber modules being divided into serial modules and parallel modules, the process tasks being a complete set of wafer processing recipes automatically performed by the semiconductor processing tool, the method comprising: when the process task is executed, determining that the failed target chamber module is a serial module or a parallel module; If the target chamber module is a serial module, adjusting transmission path information of an associated wafer which needs to pass through the target chamber module, and generating a new scheduling action sequence according to the adjusted transmission path information; If the target chamber module is a parallel module, transmitting a detained wafer detaining the target chamber module to another parallel module corresponding to the target chamber module, and generating a new scheduling action sequence for the detained wafer; Continuing to execute all the process tasks according to the newly generated scheduling action sequence; Wherein the semiconductor processing apparatus includes a wafer cassette, the adjusting of the transfer path information of the associated wafer required to pass through the target chamber module includes: Determining the current transmission position of the associated wafer; If the current transmission position is in front of the target chamber module, deleting the information of the associated wafer from the process task, and setting the calling state of the associated wafer to be a non-calling state; creating a transmission path for transmitting the associated wafer from the current transmission position to the wafer box, and obtaining the adjusted transmission path information; and if the current transmission position is behind the target chamber module, not adjusting the transmission path information of the related wafer.
  2. 2. The method of claim 1, wherein each of the chamber modules has a corresponding step number in a corresponding transfer path for each wafer, the determining the current transfer location of the associated wafer comprising: acquiring the number information of the current step of the related wafer; and determining the current transmission position of the associated wafer according to the current step number information.
  3. 3. The method of claim 1, wherein adjusting the transfer path information of the associated wafer according to the current transfer position further comprises: And if the current transmission position is the starting position of the associated wafer, deleting the information of the associated wafer from the process task, and setting the calling state of the associated wafer to be a non-calling state, wherein the information of the associated wafer comprises the transmission path information of the associated wafer.
  4. 4. The method as recited in claim 1, further comprising: And if the target chamber module is a parallel module, and the mechanical arm associated with the target chamber module and the other parallel module corresponding to the target chamber module meet the condition of transferring the detained wafer from the target chamber module to the other parallel module corresponding to the target chamber module, suspending executing the process task.
  5. 5. The method as recited in claim 1, further comprising: If the target chamber module is a parallel module, deleting the information of the detained wafer from the process task, and setting the calling state of the detained wafer to be a non-calling state; The deletion information is recorded.
  6. 6. The method of claim 5, wherein the transferring the stranded wafer stranded in the target chamber module to another parallel module corresponding to the target chamber module and generating a new scheduling action sequence for the stranded wafer comprises: After the retained wafer is transmitted to the other parallel module for processing, the information of the retained wafer is re-added into the process task according to the deleting information; Setting the calling state of the detained wafer to be a callable state; generating a new scheduling action sequence for the detained wafer.
  7. 7. A semiconductor processing apparatus comprising a wafer cassette, a plurality of chamber modules for performing processing tasks on wafers, the plurality of chamber modules being divided into serial modules and parallel modules, the processing tasks being a complete set of wafer processing recipes automatically performed by the semiconductor processing apparatus, the semiconductor processing apparatus further comprising: The system comprises a controller, a target chamber module, a scheduling action sequence and a scheduling action sequence, wherein the controller is used for determining that a failed target chamber module is a serial module or a parallel module when executing the process task, adjusting transmission path information of an associated wafer which needs to pass through the target chamber module if the target chamber module is the serial module and generating a new scheduling action sequence according to the adjusted transmission path information; The controller is further configured to determine a current transmission position of the associated wafer, delete information of the associated wafer from the process task and set a calling state of the associated wafer to an non-calling state if the current transmission position is before the target chamber module, create a transmission path for transmitting the associated wafer from the current transmission position to the wafer cassette, and obtain the adjusted transmission path information, and if the current transmission position is after the target chamber module, not adjust the transmission path information of the associated wafer.

Description

Process fault processing method and semiconductor process equipment Technical Field The present invention relates to the field of semiconductor technology, and in particular, to a process fault handling method and a semiconductor process apparatus. Background When the semiconductor process equipment executes the process task, if the process fault occurs, job (process task) is terminated, the subsequent actions thereof are cleared, job is also deleted by the system, thus causing wafer retention, the influence of incomplete process task and the like, and manual intervention and manual recovery are required. The processing mode reduces the automation degree of the semiconductor process equipment and greatly reduces the production efficiency of the equipment. Disclosure of Invention In view of the foregoing, embodiments of the present invention have been developed to provide a process fault handling method and corresponding semiconductor processing apparatus that overcome, or at least partially solve, the foregoing problems. In order to solve the above-mentioned problems, an embodiment of the present invention discloses a process fault handling method applied to a semiconductor process apparatus, the semiconductor process apparatus includes a plurality of chamber modules for performing process tasks on a wafer, and the plurality of chamber modules are divided into a serial module and a parallel module, the method includes: when the process task is executed, determining that the failed target chamber module is a serial module or a parallel module; If the target chamber module is a serial module, adjusting transmission path information of an associated wafer which needs to pass through the target chamber module, and generating a new scheduling action sequence according to the adjusted transmission path information; If the target chamber module is a parallel module, transmitting a detained wafer detaining the target chamber module to another parallel module corresponding to the target chamber module, and generating a new scheduling action sequence for the detained wafer; and continuing to execute the process task according to the newly generated scheduling action sequence. Optionally, the adjusting the transmission path information of the associated wafer passing through the target chamber module includes: Determining the current transmission position of the associated wafer; And adjusting the transmission path information of the associated wafer according to the current transmission position. Optionally, each of the chamber modules has a corresponding step number in a corresponding transmission path of each wafer, and the determining the current transmission position of the associated wafer includes: acquiring the number information of the current step of the related wafer; and determining the current transmission position of the associated wafer according to the current step number information. Optionally, the adjusting the transmission path information of the associated wafer according to the current transmission position includes: And if the current transmission position is the starting position of the associated wafer, deleting the information of the associated wafer from the process task, and setting the calling state of the associated wafer to be a non-calling state, wherein the information of the associated wafer comprises the transmission path information of the associated wafer. Optionally, the semiconductor processing apparatus includes a wafer box, and the adjusting the transmission path information of the associated wafer according to the current transmission position includes: if the current transmission position is in front of the target chamber module, deleting the information of the associated wafer from the process task, and setting the calling state of the associated wafer to be a non-calling state; And creating a transmission path for transmitting the associated wafer from the current transmission position to the wafer box, and obtaining the adjusted transmission path information. Optionally, the adjusting the transmission path information of the associated wafer according to the current transmission position includes: and if the current transmission position is behind the target chamber module, not adjusting the transmission path information of the related wafer. Optionally, the method further comprises: And if the target chamber module is a parallel module, and the mechanical arm associated with the target chamber module and the other parallel module corresponding to the target chamber module meet the condition of transferring the detained wafer from the target chamber module to the other parallel module corresponding to the target chamber module, suspending executing the process task. Optionally, the method further comprises: If the target chamber module is a parallel module, deleting the information of the detained wafer from the process task, and setting the calling state of the detained w